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1. 发明授权

US09009540B2 Memory subsystem command bus stress testing 有权
标题翻译：内存子系统命令总线压力测试
公开(公告)号：US09009540B2
公开(公告)日：2015-04-14
申请号：US13706196
申请日：2012-12-05
申请人： Christopher P. Mozak , Theodore Z. Schoenborn , James M. Shehadi , David G. Ellis , Tomer Levy , Zvika Greenfield
发明人： Christopher P. Mozak , Theodore Z. Schoenborn , James M. Shehadi , David G. Ellis , Tomer Levy , Zvika Greenfield
IPC分类号： G06F11/00 , G06F11/263 , G11C29/02 , G11C29/06 , G11C29/52
CPC分类号： G06F11/263 , G11C29/02 , G11C29/025 , G11C29/06 , G11C29/52
摘要： A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.
摘要翻译：存储器子系统包括耦合到存储器控制器和存储器件之间的命令总线的逻辑缓冲器。逻辑缓冲区检测到存储器控制器将命令总线置于存储器控制器不使用有效的可执行存储器设备命令驱动命令总线的状态。响应于检测到命令总线的状态，逻辑缓冲器产生信号模式，并且在存储器控制器的调度器之后在命令总线上注入信号模式以用信号模式驱动命令总线。

2. 发明申请

US20140157053A1 MEMORY SUBSYSTEM DATA BUS STRESS TESTING 有权
标题翻译：记忆子系统数据总线应力测试
公开(公告)号：US20140157053A1
公开(公告)日：2014-06-05
申请号：US13706177
申请日：2012-12-05
申请人： CHRISTOPHER P. MOZAK , Theodore Z. Schoenborn , James M. Shehadi , David G. Ellis
发明人： CHRISTOPHER P. MOZAK , Theodore Z. Schoenborn , James M. Shehadi , David G. Ellis
IPC分类号： G11C29/10
CPC分类号： G11C29/02 , G11C29/022 , G11C29/06 , G11C29/36 , G11C29/50012 , G11C29/52
摘要： A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.
摘要翻译：存储器子系统包括存储器控制器的测试信号发生器，其响应于存储器控制器接收测试事务而产生测试数据信号。测试事务指示在相关联的存储设备上执行的一个或多个I / O操作。测试信号发生器可以从各种不同的模式发生器产生数据信号。存储器控制器调度器调度测试数据信号模式，并将其发送到存储器件。然后，存储器件可以执行I / O操作来实现测试事务。存储器控制器可以读取写入存储器件的特定地址的数据，并将回读数据与预期数据进行比较。当回读数据和预期数据不匹配时，存储器控制器可以记录错误。该错误可以包括错误的具体地址，特定数据和/或编码数据。

3. 发明授权

US08868992B2 Robust memory link testing using memory controller 有权
标题翻译：使用内存控制器的强大的内存链接测试
公开(公告)号：US08868992B2
公开(公告)日：2014-10-21
申请号：US12651252
申请日：2009-12-31
申请人： Bryan L. Spry , Theodore Z. Schoenborn , Philip Abraham , Christopher P. Mozak , David G. Ellis , Jay J. Nejedlo , Bruce Querbach , Zvika Greenfield , Rony Ghattas , Jayasekhar Tholiyil , Charles D. Lucas , Christopher E. Yunker
发明人： Bryan L. Spry , Theodore Z. Schoenborn , Philip Abraham , Christopher P. Mozak , David G. Ellis , Jay J. Nejedlo , Bruce Querbach , Zvika Greenfield , Rony Ghattas , Jayasekhar Tholiyil , Charles D. Lucas , Christopher E. Yunker
IPC分类号： G06F11/00 , G11C29/08
CPC分类号： G11C29/08 , G11C29/10 , G11C29/44
摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
摘要翻译：引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。还公开了地址图案生成电路。

4. 发明申请

US20140157055A1 MEMORY SUBSYSTEM COMMAND BUS STRESS TESTING 有权
标题翻译：记忆子系统命令总线应力测试
公开(公告)号：US20140157055A1
公开(公告)日：2014-06-05
申请号：US13706196
申请日：2012-12-05
申请人： CHRISTOPHER P. MOZAK , Thoedore Z. Schoenborn , James M. Shehadi , David G. Ellis , Tomer Levy , Zvika Greenfield
发明人： CHRISTOPHER P. MOZAK , Thoedore Z. Schoenborn , James M. Shehadi , David G. Ellis , Tomer Levy , Zvika Greenfield
IPC分类号： G06F11/263
CPC分类号： G06F11/263 , G11C29/02 , G11C29/025 , G11C29/06 , G11C29/52
摘要： A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.
摘要翻译：存储器子系统包括耦合到存储器控制器和存储器件之间的命令总线的逻辑缓冲器。逻辑缓冲区检测到存储器控制器将命令总线置于存储器控制器不使用有效的可执行存储器设备命令驱动命令总线的状态。响应于检测到命令总线的状态，逻辑缓冲器产生信号模式，并且在存储器控制器的调度器之后在命令总线上注入信号模式以用信号模式驱动命令总线。

5. 发明授权

US07464307B2 High performance serial bus testing methodology 有权
标题翻译：高性能串行总线测试方法
公开(公告)号：US07464307B2
公开(公告)日：2008-12-09
申请号：US10396071
申请日：2003-03-25
申请人： Jay J. Nejedlo , Mike Wiznerowicz , David G. Ellis , Richard J. Glass , Andrew W. Martwick , Theodore Z. Schoenborn
发明人： Jay J. Nejedlo , Mike Wiznerowicz , David G. Ellis , Richard J. Glass , Andrew W. Martwick , Theodore Z. Schoenborn
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/3187 , G01R31/31717 , H04L1/242
摘要： According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.
摘要翻译：根据一个实施例，公开了内置自检（IBIST）架构/方法。 IBIST提供测试发射机和接收机组件之间的互连（例如总线）的功能。 IBIST架构包括一个模式生成器和一个模式检查器。模式检查器操作以将接收到的多个比特（对于模式生成器）与先前存储的多个比特进行比较。

6. 发明申请

US20150187439A1 INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR 有权
标题翻译：集成电路缺陷检测和维修
公开(公告)号：US20150187439A1
公开(公告)日：2015-07-02
申请号：US14141239
申请日：2013-12-26
申请人： Bruce Querbach , Theodore Z. Schoenborn , David J. Zimmerman , David G. Ellis , Christopher W. Hampson , Ifar Wan , Yulan Zhang , Ramakrishna Mallela , William K. Lui
发明人： Bruce Querbach , Theodore Z. Schoenborn , David J. Zimmerman , David G. Ellis , Christopher W. Hampson , Ifar Wan , Yulan Zhang , Ramakrishna Mallela , William K. Lui
IPC分类号： G11C29/36 , G06F11/263
CPC分类号： G11C29/36 , G06F11/263 , G06F11/27 , G11C11/406 , G11C29/10 , G11C29/4401 , G11C29/72 , G11C29/78 , G11C2029/4402
摘要： In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. Other aspects are described herein.
摘要翻译：根据本说明书，装置包括内部缺陷检测和修复电路，其包括内置于装置内的自检逻辑电路和内置在装置内的自修复逻辑电路。在一个实施例中，内置自检逻辑电路可以被配置为自动识别存储器中的有缺陷的存储器单元。在识别一个或多个有缺陷的存储器单元时，内置的自修复逻辑电路可以被配置为通过用存储器内的备用单元替换有缺陷的单元来自动修复有缺陷的存储单元。本文描述了其它方面。

7. 发明申请

US20140281763A1 METHOD, APPARATUS, AND SYSTEM FOR MEASUREMENT OF NOISE STATISTICS AND BIT ERROR RATIO ESTIMATION 有权
标题翻译：用于测量噪声统计和位错误比率估计的方法，装置和系统
公开(公告)号：US20140281763A1
公开(公告)日：2014-09-18
申请号：US13842320
申请日：2013-03-15
申请人： Adee O. Ran , Amir Mezer , Ophir Gazinski , Sanjay R. Ravi , David G. Ellis , Stephen J. Peters , Jeffrey M. Shuey
发明人： Adee O. Ran , Amir Mezer , Ophir Gazinski , Sanjay R. Ravi , David G. Ellis , Stephen J. Peters , Jeffrey M. Shuey
IPC分类号： G06F11/07
CPC分类号： H04L1/203
摘要： A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ration determined for a device.
摘要翻译：从第一限幅元件和第二限幅元件的装置接收采样电压。基于样本电压确定第一限幅元件的判定，并根据采样电压与第二限幅元件的判定进行比较。第二限幅元件的决定是从采样电压与第二限幅元件的参考电压的比较产生的。比较决策可以是为设备确定的软错误比例的基础。

8. 发明授权

US6119195A Virtualizing serial bus information point by address mapping via a parallel port 有权
标题翻译：通过并行端口通过地址映射虚拟化串行总线信息
公开(公告)号：US6119195A
公开(公告)日：2000-09-12
申请号：US128959
申请日：1998-08-04
申请人： David G. Ellis , Gene A. Frederiksen
发明人： David G. Ellis , Gene A. Frederiksen
IPC分类号： G06F13/38 , G06F13/00 , G06F13/40
CPC分类号： G06F13/385
摘要： The present invention is a method and apparatus for virtualizing a serial bus information source/sink point of a serial bus device into an address space of a processor. A register unit is coupled to a parallel port device to support a serial bus transaction between the processor and the serial bus device. The register unit has a plurality of registers which are mapped into the address space of the processor via the parallel port device. One of the plurality of registers corresponding to the serial bus information source/sink point. A control circuit is coupled to the register unit to allow the processor to access the information source/sink point via the parallel port device.
摘要翻译：本发明是用于将串行总线设备的串行总线信息源/汇点虚拟化到处理器的地址空间中的方法和装置。寄存器单元耦合到并行端口设备以支持处理器和串行总线设备之间的串行总线事务。寄存器单元具有经由并行端口装置映射到处理器的地址空间的多个寄存器。多个寄存器中的一个对应于串行总线信息源/汇点。控制电路耦合到寄存器单元，以允许处理器经由并行端口设备访问信息源/汇点。

9. 发明授权

US07185045B2 Ethernet interface device for reporting status via common industrial protocols 有权
标题翻译：以太网接口设备，用于通过通用工业协议报告状态
公开(公告)号：US07185045B2
公开(公告)日：2007-02-27
申请号：US10195915
申请日：2002-07-15
申请人： David G. Ellis , Steven A. Schoenberg
发明人： David G. Ellis , Steven A. Schoenberg
IPC分类号： H04L12/14
CPC分类号： H04L43/50 , H04L49/351 , H04L49/354
摘要： An Ethernet interface device, and associated system and method, for reporting the status information data of Ethernet devices through common industrial protocols. The Ethernet interface device provides operational connections between one or more Ethernet devices and one or more independent networks. The Ethernet interface device also monitors an Ethernet connection path, and produces status data indicative of the operational status of the connection path and the devices connected along the path. This status data is received by the Ethernet interface device, where it is manipulated into a format recognizable by common industrial protocols.
摘要翻译：一种以太网接口设备及相关系统和方法，用于通过通用工业协议报告以太网设备的状态信息数据。以太网接口设备提供一个或多个以太网设备与一个或多个独立网络之间的操作连接。以太网接口设备还监视以太网连接路径，并产生指示连接路径的操作状态和沿路径连接的设备的状态数据。该状态数据由以太网接口设备接收，其被操纵成通过通用工业协议可识别的格式。

10. 发明授权

US06191713B1 Conversion between serial bus cycles and parallel port commands using a state machine 有权
标题翻译：使用状态机在串行总线周期和并行端口命令之间进行转换
公开(公告)号：US06191713B1
公开(公告)日：2001-02-20
申请号：US09128946
申请日：1998-08-04
申请人： David G. Ellis , Gene A. Frederiksen
发明人： David G. Ellis , Gene A. Frederiksen
IPC分类号： H03M900
CPC分类号： G06F13/4027
摘要： The present invention is directed to a method and apparatus for converting between serial bus cycles and parallel port commands. A serial bus processor processes a serial bus transaction which is represented by the serial bus cycles and is responsive to the parallel port commands. A state machine circuit is coupled to the serial bus processor to provide a plurality of states corresponding to the serial bus transaction. The state machine circuit transitions from one of the states to any one of the states in response to a change condition asserted by a state signal.
摘要翻译：本发明涉及一种用于在串行总线周期和并行端口命令之间进行转换的方法和装置。串行总线处理器处理由串行总线周期表示的串行总线事务，并响应于并行端口命令。状态机电路耦合到串行总线处理器以提供对应于串行总线事务的多个状态。响应于由状态信号确定的改变状态，状态机电路从状态之一转换到状态中的任一状态。

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