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1. 发明授权

US08868992B2 Robust memory link testing using memory controller 有权
标题翻译：使用内存控制器的强大的内存链接测试
公开(公告)号：US08868992B2
公开(公告)日：2014-10-21
申请号：US12651252
申请日：2009-12-31
申请人： Bryan L. Spry , Theodore Z. Schoenborn , Philip Abraham , Christopher P. Mozak , David G. Ellis , Jay J. Nejedlo , Bruce Querbach , Zvika Greenfield , Rony Ghattas , Jayasekhar Tholiyil , Charles D. Lucas , Christopher E. Yunker
发明人： Bryan L. Spry , Theodore Z. Schoenborn , Philip Abraham , Christopher P. Mozak , David G. Ellis , Jay J. Nejedlo , Bruce Querbach , Zvika Greenfield , Rony Ghattas , Jayasekhar Tholiyil , Charles D. Lucas , Christopher E. Yunker
IPC分类号： G06F11/00 , G11C29/08
CPC分类号： G11C29/08 , G11C29/10 , G11C29/44
摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.
摘要翻译：引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。还公开了地址图案生成电路。

2. 发明授权

US09009540B2 Memory subsystem command bus stress testing 有权
标题翻译：内存子系统命令总线压力测试
公开(公告)号：US09009540B2
公开(公告)日：2015-04-14
申请号：US13706196
申请日：2012-12-05
申请人： Christopher P. Mozak , Theodore Z. Schoenborn , James M. Shehadi , David G. Ellis , Tomer Levy , Zvika Greenfield
发明人： Christopher P. Mozak , Theodore Z. Schoenborn , James M. Shehadi , David G. Ellis , Tomer Levy , Zvika Greenfield
IPC分类号： G06F11/00 , G06F11/263 , G11C29/02 , G11C29/06 , G11C29/52
CPC分类号： G06F11/263 , G11C29/02 , G11C29/025 , G11C29/06 , G11C29/52
摘要： A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.
摘要翻译：存储器子系统包括耦合到存储器控制器和存储器件之间的命令总线的逻辑缓冲器。逻辑缓冲区检测到存储器控制器将命令总线置于存储器控制器不使用有效的可执行存储器设备命令驱动命令总线的状态。响应于检测到命令总线的状态，逻辑缓冲器产生信号模式，并且在存储器控制器的调度器之后在命令总线上注入信号模式以用信号模式驱动命令总线。

3. 发明授权

US08819474B2 Active training of memory command timing 有权
标题翻译：主动训练存储器命令时序
公开(公告)号：US08819474B2
公开(公告)日：2014-08-26
申请号：US12417828
申请日：2009-04-03
申请人： Theodore Z. Schoenborn , John V. Lovelace , Christopher P. Mozak , Bryan L. Spry
发明人： Theodore Z. Schoenborn , John V. Lovelace , Christopher P. Mozak , Bryan L. Spry
IPC分类号： G06F1/12
CPC分类号： G06F13/4243 , G06F13/1689
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于存储器命令定时的主动训练的系统，方法和装置。在一些实施例中，使用存储器模块和存储器控制器之间的主动反馈主动地训练CMD / CTL定时。描述和要求保护其他实施例。

4. 发明申请

US20100257397A1 ACTIVE TRAINING OF MEMORY COMMAND TIMING 有权
标题翻译：主动培训内存命令时序
公开(公告)号：US20100257397A1
公开(公告)日：2010-10-07
申请号：US12417828
申请日：2009-04-03
申请人： Theodore Z. Schoenborn , John V. Lovelace , Christopher P. Mozak , Bryan L. Spry
发明人： Theodore Z. Schoenborn , John V. Lovelace , Christopher P. Mozak , Bryan L. Spry
IPC分类号： G06F1/12 , G06F13/00
CPC分类号： G06F13/4243 , G06F13/1689
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于存储器命令定时的主动训练的系统，方法和装置。在一些实施例中，使用存储器模块和存储器控制器之间的主动反馈主动地训练CMD / CTL定时。描述和要求保护其他实施例。

5. 发明授权

US08938573B2 Row hammer condition monitoring 有权
标题翻译：行锤状态监测
公开(公告)号：US08938573B2
公开(公告)日：2015-01-20
申请号：US13539417
申请日：2012-06-30
申请人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
发明人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
IPC分类号： G06F12/06 , G11C11/406 , G06F11/30
CPC分类号： G06F11/3037 , G06F11/004 , G06F11/3471 , G06F2201/81 , G06F2201/88 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.
摘要翻译：系统监视对特定行存储器的数据访问，以确定是否存在行锤条件。该系统可以监视所访问的存储行，以确定对任何行的访问次数是否超过与物理上与高访问行相邻的存储体上的数据损坏风险相关联的阈值。基于监视，存储器控制器可以确定对行的访问次数是否超过阈值，并且指示访问计数达到阈值的行的地址信息。

6. 发明授权

US09236110B2 Row hammer refresh command 有权
公开(公告)号：US09236110B2
公开(公告)日：2016-01-12
申请号：US13539415
申请日：2012-06-30
申请人： Kuljit S. Bains , John B. Halbert , Christopher P. Mozak , Theodore Z. Schoenborn , Zvika Greenfield
发明人： Kuljit S. Bains , John B. Halbert , Christopher P. Mozak , Theodore Z. Schoenborn , Zvika Greenfield
IPC分类号： G06F12/12 , G11C11/406
CPC分类号： G11C11/4091 , G06F3/0619 , G06F3/0659 , G06F3/0673 , G06F2212/7211 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

7. 发明申请

US20140006704A1 ROW HAMMER CONDITION MONITORING 有权
标题翻译： ROW HAMMER状态监测
公开(公告)号：US20140006704A1
公开(公告)日：2014-01-02
申请号：US13539417
申请日：2012-06-30
申请人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
发明人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
IPC分类号： G06F11/30 , G11C11/406
CPC分类号： G06F11/3037 , G06F11/004 , G06F11/3471 , G06F2201/81 , G06F2201/88 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.
摘要翻译：系统监视对特定行存储器的数据访问，以确定是否存在行锤条件。该系统可以监视所访问的存储行，以确定对任何行的访问次数是否超过与物理上与高访问行相邻的存储体上的数据损坏风险相关联的阈值。基于监视，存储器控制器可以确定对行的访问次数是否超过阈值，并且指示访问计数达到阈值的行的地址信息。

8. 发明申请

US20140006703A1 ROW HAMMER REFRESH COMMAND 有权
公开(公告)号：US20140006703A1
公开(公告)日：2014-01-02
申请号：US13539415
申请日：2012-06-30
申请人： Kuljit S. Bains , John B. Halbert , Christopher P. Mozak , Theodore Z. Schoenborn , Zvika Greenfield
发明人： Kuljit S. Bains , John B. Halbert , Christopher P. Mozak , Theodore Z. Schoenborn , Zvika Greenfield
IPC分类号： G11C11/406
CPC分类号： G11C11/4091 , G06F3/0619 , G06F3/0659 , G06F3/0673 , G06F2212/7211 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

9. 发明授权

US07464307B2 High performance serial bus testing methodology 有权
标题翻译：高性能串行总线测试方法
公开(公告)号：US07464307B2
公开(公告)日：2008-12-09
申请号：US10396071
申请日：2003-03-25
申请人： Jay J. Nejedlo , Mike Wiznerowicz , David G. Ellis , Richard J. Glass , Andrew W. Martwick , Theodore Z. Schoenborn
发明人： Jay J. Nejedlo , Mike Wiznerowicz , David G. Ellis , Richard J. Glass , Andrew W. Martwick , Theodore Z. Schoenborn
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/3187 , G01R31/31717 , H04L1/242
摘要： According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.
摘要翻译：根据一个实施例，公开了内置自检（IBIST）架构/方法。 IBIST提供测试发射机和接收机组件之间的互连（例如总线）的功能。 IBIST架构包括一个模式生成器和一个模式检查器。模式检查器操作以将接收到的多个比特（对于模式生成器）与先前存储的多个比特进行比较。

10. 发明申请

US20140157053A1 MEMORY SUBSYSTEM DATA BUS STRESS TESTING 有权
标题翻译：记忆子系统数据总线应力测试
公开(公告)号：US20140157053A1
公开(公告)日：2014-06-05
申请号：US13706177
申请日：2012-12-05
申请人： CHRISTOPHER P. MOZAK , Theodore Z. Schoenborn , James M. Shehadi , David G. Ellis
发明人： CHRISTOPHER P. MOZAK , Theodore Z. Schoenborn , James M. Shehadi , David G. Ellis
IPC分类号： G11C29/10
CPC分类号： G11C29/02 , G11C29/022 , G11C29/06 , G11C29/36 , G11C29/50012 , G11C29/52
摘要： A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.
摘要翻译：存储器子系统包括存储器控制器的测试信号发生器，其响应于存储器控制器接收测试事务而产生测试数据信号。测试事务指示在相关联的存储设备上执行的一个或多个I / O操作。测试信号发生器可以从各种不同的模式发生器产生数据信号。存储器控制器调度器调度测试数据信号模式，并将其发送到存储器件。然后，存储器件可以执行I / O操作来实现测试事务。存储器控制器可以读取写入存储器件的特定地址的数据，并将回读数据与预期数据进行比较。当回读数据和预期数据不匹配时，存储器控制器可以记录错误。该错误可以包括错误的具体地址，特定数据和/或编码数据。

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