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1. 发明授权

US5459084A Method for fabricating hetero-junction bipolar transistor having reduced base parasitic resistance 失效
标题翻译：具有降低的基极寄生电阻的异质结双极晶体管的制造方法
公开(公告)号：US5459084A
公开(公告)日：1995-10-17
申请号：US358533
申请日：1994-12-19
申请人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Oh-Joon Kwon
发明人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Oh-Joon Kwon
IPC分类号： H01L21/331 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/7378 , Y10S148/01 , Y10S148/011 , Y10S148/072
摘要： Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is fully reduced by using a metallic silicide as a base, comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region; growing a collector epitaxial layer on the buried collector region and forming a field oxide layer; selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer and an first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film thereon to form a base electrode thin film; forming a capping oxide layer of about 500 .ANG. thickness only on the base electrode thin film; forming an isolating oxide layer thereon and sequentially and selectively removing the isolating oxide layer, the capping oxide layer, the base electrode thin film and the base layer using a patterned photomask to form a pattern, the isolating oxide layer being provided to electrically isolate base and emitter; forming a side wall oxide layer at both side edges of the pattern; removing a portion of the isolating oxide layer to define an emitter region; forming a passivation layer thereon and selectively removing the passivation layer to form contact holes; and depositing a polysilicon layer doped with impurity ions in the contact holes to form electrodes.
摘要翻译：公开了通过使用金属硅化物作为基底而使基极寄生电容完全降低的异质结双极晶体管的制造方法，包括以下步骤：在硅衬底中注入杂质以形成导电的埋地集电区; 在掩埋的集电极区上生长集电极外延层并形成场氧化物层; 选择性地将杂质注入到集电极外延层中以形成集电极沉降片; 在其上依次形成基底层和第一氧化物层; 图案化第一氧化物层以限定外部碱性区域; 使用图案化氧化物层作为掩模在外部基极区域中离子注入杂质并除去图案化的氧化物层; 在其上沉积金属硅化物膜以形成基极薄膜; 仅在基极薄膜上形成约500厚度的覆盖氧化物层; 在其上形成隔离氧化物层，并使用图案化的光掩模依次选择性地去除隔离氧化物层，封盖氧化物层，基极薄膜和基层，形成图案，隔离氧化物层被提供以电隔离基极和发射器在图案的两个侧边缘处形成侧壁氧化物层; 去除所述隔离氧化物层的一部分以限定发射极区域; 在其上形成钝化层并选择性地去除钝化层以形成接触孔; 以及在所述接触孔中沉积掺杂有杂质离子的多晶硅层以形成电极。

2. 发明授权

US5798277A Method for fabricating heterojunction bipolar transistor 失效
标题翻译：异质结双极晶体管的制造方法
公开(公告)号：US5798277A
公开(公告)日：1998-08-25
申请号：US729841
申请日：1996-10-15
申请人： Byung-Ryul Ryum , Tae-Hyeon Han , Deok-Ho Cho , Soo-Min Lee , Kwang-Eui Pyun
发明人： Byung-Ryul Ryum , Tae-Hyeon Han , Deok-Ho Cho , Soo-Min Lee , Kwang-Eui Pyun
IPC分类号： H01L29/70 , H01L21/331 , H01L29/08 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7371 , Y10S148/05 , Y10S148/072
摘要： An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the base electrode polysilicon layer on the shallow trench, and forming a self-aligned base.
摘要翻译：一种用于制造异质结双极晶体管的改进方法，其包括以下步骤：在半导体衬底上形成掩埋集电极，集电极薄膜和集电极沉降片，以形成第一氧化硅膜，基极多晶硅层，氮化物在所得到的基板上暴露第一硅氧化膜的氧化膜，在暴露区域的侧面形成间隔绝缘膜，并限定激活区域，使用掩模曝光激活区域的集电极薄膜，并形成用于隔离器件的辅助横向膜，通过将离子注入到由辅助侧膜限制的活化区域的掺杂剂形成选择性集电极区域，去除辅助横向膜，在各向异性层中蚀刻暴露部分蚀刻方法，以及形成用于器件隔离的浅沟槽，形成多晶硅侧膜以具有s的高度 ame作为浅沟槽上的基极多晶硅层的高度，并形成自对准基底。

3. 发明授权

US06552374B2 Method of manufacturing bipolar device and structure thereof 失效
公开(公告)号：US06552374B2
公开(公告)日：2003-04-22
申请号：US09765499
申请日：2001-01-17
申请人： Tae-Hyeon Han , Byung Ryul Ryum , Soo-Min Lee , Deok-Ho Cho
发明人： Tae-Hyeon Han , Byung Ryul Ryum , Soo-Min Lee , Deok-Ho Cho
IPC分类号： H01L31072
CPC分类号： H01L29/66287 , H01L29/7322
摘要： Disclosed are a method for forming a base layer by epitaxial growth technology of a heterojunction bipolar device and a structure of the bipolar device manufactured by the method. The method comprises steps of depositing an insulation film containing silicon nitride on a substrate and removing a part of the insulation film to define a collector area; growing a first semiconductor in the collector area by selective epitaxial growth method to form the collector protruded over the insulation film in the form of a mushroom; forming an oxide film containing silicon dioxide on a surface of the collector protruded over the silicon nitride; selectively growing a second polycrystalline semiconductor material on only the nitride insulation film at the same height as the protruded portion of the collector to form a first base semiconductor electrode; removing an upper surface of the oxide film to expose the collector; and growing a second semiconductor containing silicon-germanium on the second polycrystalline semiconductor and the collector of the first semiconductor to form a second base semiconductor electrode on the first base semiconductor electrode and the base on the collector, thereby preventing a current leakage and a loading effect.

4. 发明授权

US06190984B1 Method for fabricating of super self-aligned bipolar transistor 失效
标题翻译：超自对准双极晶体管的制造方法
公开(公告)号：US06190984B1
公开(公告)日：2001-02-20
申请号：US09229831
申请日：1999-01-13
申请人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
发明人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
IPC分类号： H01L218222
CPC分类号： H01L29/66242
摘要： The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.
摘要翻译：本发明涉及一种用于制造能够使元件小型化的超自对准异质结双极晶体管的方法，通过采用选择性集电体外延生长工艺简化其工艺步骤，而不使用用于元件间隔离的沟槽。根据本发明，通过使用限定发射极区域和第二间隔物的掩模来导出元件之间的隔离。基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。此外，不需要基底的选择性外延生长。因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

5. 发明授权

US5696020A Method for fabricating semiconductor device isolation region using a trench mask 失效
标题翻译：使用沟槽掩模制造半导体器件隔离区域的方法
公开(公告)号：US5696020A
公开(公告)日：1997-12-09
申请号：US470479
申请日：1995-06-05
申请人： Byung-Ryul Ryum , Tae-Hyeon Han , Soo-Min Lee , Deok-Ho Cho , Jin-Young Kang
发明人： Byung-Ryul Ryum , Tae-Hyeon Han , Soo-Min Lee , Deok-Ho Cho , Jin-Young Kang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/76202
摘要： Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxide film and the silicon oxide film and removing the polysilicon film only the inactive region; performing a thermal oxidation to form a field oxide film on the inactive region; and sequentially removing the isolating layer and the polysilicon film formed on the active region. Because the active region is defined using an insulator-filled shallow trench before performing thermal oxidation, no oxygen is penetrated into the active region during the thermal oxidation, whereby a field oxide film can be formed without occurrence of a Bird's beak.
摘要翻译：公开了一种半导体器件的器件隔离方法，包括以下步骤：在硅衬底上顺序形成衬垫氧化膜，多晶硅膜和绝缘层，所述绝缘层由第一氧化硅膜，氮化膜以及顺序地形成在所述多晶硅膜上的第二氧化硅膜; 通过使用图案化的光掩模来定义有源和非活性区域; 仅在非活性区域上去除绝缘层，以暴露多晶硅膜的表面; 在有源区域上的绝缘层的两个边缘处形成侧壁，所述侧壁由氮化物膜构成; 在所述多晶硅膜的表面上沉积第三氧化硅膜; 去除侧壁并将衬底蚀刻到预定深度以形成沟槽; 将绝缘材料填充到沟槽中并将其沉积到第二氧化硅上，以形成用于隔离的绝缘膜; 同时去除第二氧化硅膜和氧化硅膜，并且仅去除多晶硅膜的非活性区域; 进行热氧化以在非活性区域上形成场氧化物膜; 并依次去除形成在有源区上的隔离层和多晶硅膜。由于在进行热氧化之前使用绝缘子填充的浅沟槽限定有源区域，所以在热氧化期间没有氧气渗透到有源区域中，由此可以形成场氧化膜而不发生鸟喙。

6. 发明授权

US5668022A Silicon-silicon-germanium heterojunction bipolar transistor fabrication method 失效
标题翻译：硅硅锗异质结双极晶体管制造方法
公开(公告)号：US5668022A
公开(公告)日：1997-09-16
申请号：US700930
申请日：1996-08-23
申请人： Deok-Ho Cho , Soo-Min Lee , Tae-Hyeon Han , Byung-Ryul Ryum , Kwang-Eui Pyun
发明人： Deok-Ho Cho , Soo-Min Lee , Tae-Hyeon Han , Byung-Ryul Ryum , Kwang-Eui Pyun
IPC分类号： H01L29/73 , H01L21/331 , H01L29/165 , H01L29/732 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/7378 , Y10S148/072
摘要： A silicon/silicon-germanium bipolar transistor fabrication method employs a metallic silicide film as an extrinsic base electrode to reduce resistance of the extrinsic base electrode, and to increase a maximum oscillation frequency and cut-off frequency due to its self-aligned structure. The fabrication method enables agglomeration to occur on the side wall of the polycrystalline silicon film connected to the metallic silicide film instead of on the interface between the metallic silicide film and the lower silicon/silicon-germanium film, and leads the extrinsic base electrode to be sandwitched by the insulator films, thereby realizing a constant resistance and also resulting in the application of integrated circuits to a mass production mechanism.
摘要翻译：硅/硅 - 锗双极晶体管制造方法使用金属硅化物膜作为外部基极，以降低外部基极的电阻，并且由于其自对准结构而增加最大振荡频率和截止频率。该制造方法可以在连接到金属硅化物膜的多晶硅膜的侧壁上而不是在金属硅化物膜和下硅/硅 - 锗膜之间的界面上发生聚集，并且引导外部基极为由绝缘体膜切割，从而实现恒定的电阻，并且还导致集成电路应用于大规模生产机构。

7. 发明授权

US5981345A Si/SiGe MOSFET and method for fabricating the same 失效
公开(公告)号：US5981345A
公开(公告)日：1999-11-09
申请号：US891013
申请日：1997-07-10
申请人： Byung-Ryul Ryum , Soo-Min Lee , Deok-Ho Cho , Tae-Hyeon Han
发明人： Byung-Ryul Ryum , Soo-Min Lee , Deok-Ho Cho , Tae-Hyeon Han
IPC分类号： H01L27/06 , H01L21/336 , H01L29/10 , H01L29/417 , H01L29/45 , H01L21/249
CPC分类号： H01L29/66477 , H01L29/1054 , H01L29/41766 , H01L29/456 , H01L29/66651
摘要： The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the problems, such as the punch-through caused by the short distance between the source region and the drain region, the decrease of the breakdown voltage between the source region and the drain region and the leakage current flowing into the bulk region beneath the channel due to the drain-induced barrier lowering. Furthermore, because the source region and the drain region are isolated from the semiconductor substrate by the lower insulation layer, the removal of the parasite junction capacitor speed up the transistor.

8. 发明授权

US5962879A Super self-aligned bipolar transistor 失效
标题翻译：超自对准双极晶体管
公开(公告)号：US5962879A
公开(公告)日：1999-10-05
申请号：US854665
申请日：1997-05-12
申请人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
发明人： Byung-Ryul Ryum , Deok-Ho Cho , Tae-Hyeon Han , Soo-Min Lee , Kwang-Eui Pyun
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.
摘要翻译：本发明涉及一种用于制造能够使元件小型化的超自对准异质结双极晶体管的方法，通过采用选择性集电体外延生长工艺简化其工艺步骤，而不使用用于元件间隔离的沟槽。根据本发明，通过使用限定发射极区域和第二间隔物的掩模来导出元件之间的隔离。基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。此外，不需要基底的选择性外延生长。因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

9. 发明授权

US06562688B2 Method of manufacturing a bipolar device 失效
标题翻译：制造双极器件的方法
公开(公告)号：US06562688B2
公开(公告)日：2003-05-13
申请号：US09747761
申请日：2000-12-21
申请人： Tae-Hyeon Han , Byung Ryul Ryum , Soo-Min Lee , Deok-Ho Cho
发明人： Tae-Hyeon Han , Byung Ryul Ryum , Soo-Min Lee , Deok-Ho Cho
IPC分类号： H01L21331
CPC分类号： H01L29/66287 , H01L29/66242
摘要： Disclosed are a method for manufacturing a homojunction or heterojunction bipolar device and a structure of the bipolar device manufactured by the method. The method comprises steps of forming a collector on a substrate including a buried collector to be contacted with the buried collector and protruded in the form of an island; depositing a collector dielectric film on the substrate on which the collector is formed; removing a protruded portion of the collector dielectric film covering the substrate; depositing a first semiconductor electrode layer on the substrate including the collector protruded over the collector dielectric film and flatting a surface of the first semiconductor electrode to expose only the collector formed of a semiconductor material and the first semiconductor electrode; and growing a base thin film including one of silicon and silicon-germanium on the substrate on which only the semiconductor material is exposed, thereby preventing the non-uniformity of a thickness of the base thin film, a contain rate of an impurity and a germanium distribution by the loading effect.
摘要翻译：公开了用于制造均质结或异质结双极器件的方法和通过该方法制造的双极器件的结构。该方法包括以下步骤：在包括与埋藏式收集器接触并以岛形式突出的埋地收集器的基板上形成集电器; 在其上形成集电极的基板上沉积集电极电介质膜; 去除覆盖所述基板的所述集电极电介质膜的突出部分; 在包括集电极电介质膜上的集电体的基板上沉积第一半导体电极层，使第一半导体电极的表面平坦化，仅露出由半导体材料形成的集电体和第一半导体电极; 并且在仅在其上仅露出半导体材料的基板上生长包括硅和硅锗之一的基底薄膜，从而防止基底薄膜的厚度不均匀，杂质含量和锗的含量通过负载效应分配。

10. 发明授权

US5874347A Method for fabricating field oxide isolation region for semiconductor devices 失效
标题翻译：半导体器件的场氧化物隔离区域的制造方法
公开(公告)号：US5874347A
公开(公告)日：1999-02-23
申请号：US688283
申请日：1996-07-29
申请人： Byung-Ryul Ryum , Tae-Hyeon Han , Soo-Min Lee , Deok-Ho Cho , Jin-Young Kang
发明人： Byung-Ryul Ryum , Tae-Hyeon Han , Soo-Min Lee , Deok-Ho Cho , Jin-Young Kang
IPC分类号： H01L21/316 , H01L21/32 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/32 , H01L21/76202
摘要： Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxide film and the silicon oxide film and removing the polysilicon film only the inactive region; performing a thermal oxidation to form a field oxide film on the inactive region; and sequentially removing the isolating layer and the polysilicon film formed on the active region. Because the active region is defined using an insulator-filled shallow trench before performing thermal oxidation, no oxygen is penetrated into the active region during the thermal oxidation, whereby a field oxide film can be formed without occurrence of a Bird's beak.
摘要翻译：公开了一种半导体器件的器件隔离方法，包括以下步骤：在硅衬底上顺序形成衬垫氧化膜，多晶硅膜和绝缘层，所述绝缘层由第一氧化硅膜，氮化膜以及顺序地形成在所述多晶硅膜上的第二氧化硅膜; 通过使用图案化的光掩模来定义有源和非活性区域; 仅在非活性区域上去除绝缘层，以暴露多晶硅膜的表面; 在有源区域上的绝缘层的两个边缘处形成侧壁，所述侧壁由氮化物膜构成; 在所述多晶硅膜的表面上沉积第三氧化硅膜; 去除侧壁并将衬底蚀刻到预定深度以形成沟槽; 将绝缘材料填充到沟槽中并将其沉积到第二氧化硅上，以形成用于隔离的绝缘膜; 同时去除第二氧化硅膜和氧化硅膜，并且仅去除多晶硅膜的非活性区域; 进行热氧化以在非活性区域上形成场氧化物膜; 并依次去除形成在有源区上的隔离层和多晶硅膜。由于在进行热氧化之前使用绝缘子填充的浅沟槽限定有源区域，所以在热氧化期间没有氧气渗透到有源区域中，由此可以形成场氧化膜而不发生鸟喙。

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