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    • 1. 发明授权
    • Thin-film transistor and method of making same
    • 薄膜晶体管及其制造方法
    • US06340610B1
    • 2002-01-22
    • US09243556
    • 1999-02-02
    • Byung-Chul AhnHyun-Sik Seo
    • Byung-Chul AhnHyun-Sik Seo
    • H01L2100
    • H01L29/42384H01L29/4908H01L29/66765H01L29/78636
    • A thin-film transistor includes a substrate and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by about 1 to 4 &mgr;m. A method of making such a thin film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layer directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.
    • 薄膜晶体管包括基板和包括具有设置在基板上的第一和第二金属层的双层结构的栅极,第一金属层比第二金属层宽约1至4微米。 制造这种薄膜晶体管的方法包括以下步骤:在衬底上沉积第一金属层,将第二金属层直接沉积在第一金属层上; 在所述第二金属层上形成具有指定宽度的光致抗蚀剂; 通过使用光致抗蚀剂作为掩模的各向同性蚀刻图案化第二金属层; 通过使用光致抗蚀剂作为掩模的各向异性蚀刻图案化第一金属层,第一金属层被蚀刻成具有指定的宽度,从而形成具有第一和第二金属层的层叠结构的栅极; 并去除光致抗蚀剂。
    • 2. 发明授权
    • Thin-film transistor and method of making same
    • 薄膜晶体管及其制造方法
    • US07176489B2
    • 2007-02-13
    • US10872527
    • 2004-06-22
    • Byung-Chul AhnHyun-Sik Seo
    • Byung-Chul AhnHyun-Sik Seo
    • H01L29/04H01L29/10H01L31/036H01L31/0376H01L31/20
    • H01L29/42384H01L29/4908H01L29/66765H01L29/78636
    • A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by 1 to 4 μm. A method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.
    • 薄膜晶体管包括基板和包括具有设置在基板上的第一和第二金属层的双层结构的栅极,第一金属层比第二金属层宽1至4微米。 制造这种薄膜晶体管的方法包括以下步骤:在衬底上沉积第一金属层,将第二金属层直接沉积在第一金属层上; 在所述第二金属层上形成具有指定宽度的光致抗蚀剂; 通过使用光致抗蚀剂作为掩模的各向同性蚀刻图案化第二金属层; 通过使用光致抗蚀剂作为掩模的各向异性蚀刻图案化第一金属层,第一金属层被蚀刻成具有指定的宽度,从而形成具有第一和第二金属层的层叠结构的栅极; 并去除光致抗蚀剂。
    • 3. 发明授权
    • Thin-film transistor and method of making same
    • 薄膜晶体管及其制造方法
    • US5905274A
    • 1999-05-18
    • US918119
    • 1997-08-27
    • Byung-Chul AhnHyun-Sik Seo
    • Byung-Chul AhnHyun-Sik Seo
    • H01L21/28H01L21/336H01L27/12H01L29/423H01L29/49H01L29/786H01L29/04H01L31/036H01L31/0376
    • H01L29/42384H01L29/4908H01L29/66765H01L29/78636
    • A thin-film transistor includes a substrate and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by about 1 to 4 .mu.m. A method of making such a thin film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layer directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.
    • 薄膜晶体管包括基板和包括具有设置在基板上的第一和第二金属层的双层结构的栅极,第一金属层比第二金属层宽约1至4μm。 制造这种薄膜晶体管的方法包括以下步骤:在衬底上沉积第一金属层,将第二金属层直接沉积在第一金属层上; 在所述第二金属层上形成具有指定宽度的光致抗蚀剂; 通过使用光致抗蚀剂作为掩模的各向同性蚀刻图案化第二金属层; 通过使用光致抗蚀剂作为掩模的各向异性蚀刻图案化第一金属层,第一金属层被蚀刻成具有指定的宽度,从而形成具有第一和第二金属层的层叠结构的栅极; 并去除光致抗蚀剂。
    • 5. 发明授权
    • Thin-film transistor
    • 薄膜晶体管
    • US06548829B2
    • 2003-04-15
    • US10154955
    • 2002-05-28
    • Byung-Chul AhnHyun-Sik Seo
    • Byung-Chul AhnHyun-Sik Seo
    • H01L2904
    • H01L29/42384H01L29/4908H01L29/66765H01L29/78636
    • A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by 1 to 4 &mgr;m. A method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.
    • 薄膜晶体管包括基板和包括具有设置在基板上的第一和第二金属层的双层结构的栅极,第一金属层比第二金属层宽1至4微米。 制造这种薄膜晶体管的方法包括以下步骤:在衬底上沉积第一金属层,将第二金属层直接沉积在第一金属层上; 在所述第二金属层上形成具有指定宽度的光致抗蚀剂; 通过使用光致抗蚀剂作为掩模的各向同性蚀刻图案化第二金属层; 通过使用光致抗蚀剂作为掩模的各向异性蚀刻图案化第一金属层,第一金属层被蚀刻成具有指定的宽度,从而形成具有第一和第二金属层的层叠结构的栅极; 并去除光致抗蚀剂。
    • 6. 发明授权
    • Array substrate including thin film transistor and method of fabricating the same
    • 阵列基板包括薄膜晶体管及其制造方法
    • US08021937B2
    • 2011-09-20
    • US12486453
    • 2009-06-17
    • Hyung-Gu RohByung-Chul AhnHee-Dong ChoiSeong-Moh SeoJun-Min Lee
    • Hyung-Gu RohByung-Chul AhnHee-Dong ChoiSeong-Moh SeoJun-Min Lee
    • H01L21/336
    • H01L27/1285H01L21/268H01L27/1288
    • A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole.
    • 制造阵列基板的方法包括:形成栅极线和连接到栅极线的栅电极; 在栅极线和栅极绝缘层上形成栅极绝缘层; 在栅电极上的栅极绝缘层上依次形成本征非晶硅图案和杂质掺杂非晶硅图案; 在栅极绝缘层上形成数据线,在掺杂杂质的非晶硅图案上的源电极和漏极之间形成数据线,该数据线与栅极线交叉以限定一个像素区域,以及源极和漏极彼此间隔开; 去除通过源极和漏极暴露的杂质掺杂非晶硅图案的一部分,以限定欧姆接触层; 通过源极和漏极将第一激光束照射到本征非晶硅图案上,以在第一部分的两侧形成包括多晶硅的第一部分和非晶硅的第二部分的有源层; 在数据线上形成钝化层,源电极和漏电极,钝化层具有暴露漏电极的漏极接触孔; 以及在所述像素区域中的钝化层上形成像素电极,所述像素电极通过所述漏极接触孔与所述漏电极连接。
    • 7. 发明授权
    • Method of fabricating array substrate
    • 阵列基板的制作方法
    • US07910414B2
    • 2011-03-22
    • US12591501
    • 2009-11-20
    • Hee-Dong ChoiSang-Gul LeeSeong-Moh SeoJun-Min LeeByung-Chul Ahn
    • Hee-Dong ChoiSang-Gul LeeSeong-Moh SeoJun-Min LeeByung-Chul Ahn
    • H01L21/00H01L21/84
    • H01L27/1274H01L27/1214H01L27/1288H01L29/4908
    • A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.
    • 制造阵列基板的方法包括在基板上依次形成第一金属层,第一无机绝缘层和本征非晶硅层,所述第一金属层包括第一金属材料层和第二金属材料层; 结晶本征非晶硅; 形成栅电极,栅极线,栅绝缘层和有源层; 形成包括分别暴露有源层的两侧的第一和第二接触孔的层间绝缘层; 形成分别接触有源层的两侧的第一和第二欧姆接触图案,源电极,漏电极和连接源电极的数据线; 在源极上形成钝化层,漏电极; 以及在所述钝化层上形成像素电极并与所述漏电极接触。