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1. 发明授权

US08228282B2 Gate driving circuit, display apparatus having the same, and method thereof 有权
标题翻译：栅极驱动电路，具有该栅极驱动电路的显示装置及其方法
公开(公告)号：US08228282B2
公开(公告)日：2012-07-24
申请号：US11928466
申请日：2007-10-30
申请人： Byoung-Sun Na , Dong-Hyeon Ki , Min-Cheol Lee , Soon-Il Ahn
发明人： Byoung-Sun Na , Dong-Hyeon Ki , Min-Cheol Lee , Soon-Il Ahn
IPC分类号： G09G3/36
CPC分类号： G11C19/28 , G09G3/3677 , G09G2320/0219 , G09G2320/041
摘要： In a gate driving circuit and a display apparatus having the gate driving circuit, a pull-up transistor of a present stage among plural stages, which are connected one after another to each other and sequentially output a gate signal, pulls up a present gate signal output through an output terminal to a gate-on voltage. A buffer transistor is connected to a control terminal of the pull-up transistor to receive a previous output signal from a previous stage and to turn on the pull-up transistor. The buffer transistor has a chargeability that is about two times or greater than the chargeability of the pull-up transistor. Thus, the size of the pull-up transistor may be reduced, thereby preventing a malfunction of the gate driving circuit when the gate driving circuit is operated under conditions of high temperature or low temperature.
摘要翻译：在具有栅极驱动电路的栅极驱动电路和显示装置中，将多个相互依次连接并依次输出栅极信号的多级中的当前级的上拉晶体管拉起当前的栅极信号通过输出端子输出到栅极导通电压。缓冲晶体管连接到上拉晶体管的控制端，以接收来自前一级的先前输出信号并接通上拉晶体管。缓冲晶体管具有的电荷率约为上拉晶体管的充电能力的两倍或更大。因此，可以减小上拉晶体管的尺寸，从而当栅极驱动电路在高温或低温条件下工作时，防止栅极驱动电路的故障。

2. 发明授权

US08558776B2 Display panel and display apparatus having the same 有权
标题翻译：显示面板和具有该显示面板的显示装置
公开(公告)号：US08558776B2
公开(公告)日：2013-10-15
申请号：US11999329
申请日：2007-12-04
申请人： Min-Cheol Lee , Hee-Bum Park , Yong-Soon Lee , Seung-Soo Baek , Sang-Jin Jeon
发明人： Min-Cheol Lee , Hee-Bum Park , Yong-Soon Lee , Seung-Soo Baek , Sang-Jin Jeon
IPC分类号： G09G3/36
CPC分类号： G09G3/3611 , G09G3/3677 , G09G2320/0223
摘要： In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.
摘要翻译：在具有显示面板的显示面板和显示装置中，显示面板包括阵列和相对的基板。阵列基板包括显示器和外围区域。栅极和源极线形成在显示区域中。在周边区域中形成栅极驱动部分和第一和第二时钟线。栅极驱动部分将栅极信号输出到栅极线。第一和第二时钟线分别将第一和第二时钟信号发送到门驱动部分。相对的衬底与阵列衬底组合并且包括公共电极层。公共电极层具有图案化以暴露第一和第二时钟线的开口部分。第一和第二时钟线的暴露部分具有基本上相同的面积。因此，可以使门信号的延迟最小化并且可以防止门信号的失真。

3. 发明申请

US20090021509A1 FLAT PANEL CRYSTAL DISPLAY EMPLOYING SIMULTANEOUS CHARGING OF MAIN AND SUBSIDIARY PIXEL ELECTRODES 有权
标题翻译：平板显示器采用主要和附属像素电极的同时充电
公开(公告)号：US20090021509A1
公开(公告)日：2009-01-22
申请号：US12175961
申请日：2008-07-18
申请人： Min-Cheol Lee , Seung-Hwan Moon
发明人： Min-Cheol Lee , Seung-Hwan Moon
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2300/0443 , G09G2300/0447 , G09G2310/0205
摘要： A display system includes a display panel having a plurality of pixel units, each of the pixel units having first and second divided pixel parts; a first driver for applying a first gate signal to the first divided pixel part; and a second driver for applying a second gate signal to the second divided pixel part, wherein the first and second drivers are integrally formed in the display panel and apply the first and second gate signals to be at least partially time-overlapped through independent driving.
摘要翻译：显示系统包括具有多个像素单元的显示面板，每个像素单元具有第一和第二分割像素部分; 用于将第一栅极信号施加到第一分割像素部分的第一驱动器; 以及第二驱动器，用于将第二栅极信号施加到第二分割像素部分，其中第一和第二驱动器一体地形成在显示面板中，并且通过独立驱动将第一和第二栅极信号施加至少部分时间重叠。

4. 发明授权

US08310432B2 Gate driving circuit, display device having the same, and method for manufacturing the display device 有权
标题翻译：栅极驱动电路，具有该栅极驱动电路的显示装置及其制造方法
公开(公告)号：US08310432B2
公开(公告)日：2012-11-13
申请号：US12509679
申请日：2009-07-27
申请人： Min-Cheol Lee , Hyung-Guel Kim , Jin Jeon
发明人： Min-Cheol Lee , Hyung-Guel Kim , Jin Jeon
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G02F1/1368 , G11C19/184 , G11C19/28
摘要： A gate driving circuit having improved driving capability and maintaining reliability even after a prolonged period of use includes a shift register having a plurality of stages cascaded to one another, each of the plurality of stages including a pull-up unit, a pull-down unit, a discharging unit, and a holding unit, wherein at least one of the discharging unit and the holding unit includes an amorphous silicon thin film transistor and a polysilicon thin film transistor connected in parallel to each other.
摘要翻译：具有改善的驱动能力并且即使在长时间使用之后也保持可靠性的栅极驱动电路包括具有彼此级联的多个级的移位寄存器，所述多个级中的每一级包括上拉单元，下拉单元放电单元和保持单元，其中放电单元和保持单元中的至少一个包括彼此并联连接的非晶硅薄膜晶体管和多晶硅薄膜晶体管。

5. 发明授权

US07936332B2 Gate driving circuit having reduced ripple effect and display apparatus having the same 有权
标题翻译：具有减小的纹波效应的栅极驱动电路和具有该纹波效应的显示装置
公开(公告)号：US07936332B2
公开(公告)日：2011-05-03
申请号：US11763144
申请日：2007-06-14
申请人： Min-Cheol Lee , Seung-Hwan Moon
发明人： Min-Cheol Lee , Seung-Hwan Moon
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G2310/0286
摘要： In a gate driving circuit and a display apparatus, the gate driving circuit comprises a plurality of stages. At least one of the stages comprises a pull-up section responsive to a first node signal; a pull-down section responsive to a second input signal; a discharging section discharging the first node signal in response to the second input signal; a first holding section responsive to the first clock signal, maintaining the first node signal at the off-voltage; and a second holding section responsive to the second clock signal, maintaining the first node signal at the off-voltage. The second holding section has a greater transistor width-to-length ratio than the first holding section. Therefore, an abnormal gate-on signal is less likely to occur, reducing driving defects of the display apparatus.
摘要翻译：在栅极驱动电路和显示装置中，栅极驱动电路包括多个级。至少一个级包括响应于第一节点信号的上拉部分; 响应于第二输入信号的下拉部分; 放电部分，响应于所述第二输入信号而放电所述第一节点信号; 响应于所述第一时钟信号的第一保持部分，将所述第一节点信号保持在所述截止电压; 以及响应于第二时钟信号的第二保持部分，将第一节点信号保持在截止电压。第二保持部具有比第一保持部更大的晶体管宽度比。因此，不太可能发生异常的接通信号，减少了显示装置的驱动缺陷。

6. 发明申请

US20060274009A1 Liquid crystal display and method thereof 有权
标题翻译：液晶显示器及其方法
公开(公告)号：US20060274009A1
公开(公告)日：2006-12-07
申请号：US11445412
申请日：2006-06-01
申请人： Min-Cheol Lee
发明人： Min-Cheol Lee
IPC分类号： G09G3/36
CPC分类号： G09G3/3659 , G02F1/136213 , G09G3/3648 , G09G3/3655 , G09G2300/0443 , G09G2320/028
摘要： A liquid crystal display includes a first gate electrode, a storage electrode having a body and an extension, a first semiconductor formed on a gate insulating layer, a first drain electrode formed on the first semiconductor, separated from a first source electrode, and having an end portion overlapping the first gate electrode, and an expansion overlapping the body of the storage electrode and distanced from the end portion with a connection connecting the end portion and the expansion and overlapping the extension of the storage electrode, a passivation layer having a contact hole exposing the expansion of the first drain electrode, and a first field-generating electrode connected to the first drain electrode through the contact hole.
摘要翻译：液晶显示器包括第一栅电极，具有本体和延伸部的存储电极，形成在栅极绝缘层上的第一半导体，形成在第一半导体上的第一漏电极，与第一源电极分离，并且具有端部与第一栅电极重叠，并且膨胀与存储电极的主体重叠并且与端部间隔开，连接端部和扩展部并且与存储电极的延伸部重叠;钝化层，具有接触孔暴露第一漏电极的膨胀，以及通过接触孔连接到第一漏电极的第一场产生电极。

7. 发明授权

US08400390B2 Gate driving device and liquid crystal display having the same 有权
标题翻译：栅极驱动装置和具有其的液晶显示器
公开(公告)号：US08400390B2
公开(公告)日：2013-03-19
申请号：US12645902
申请日：2009-12-23
申请人： Min-Cheol Lee , Seung-Hwan Moon
发明人： Min-Cheol Lee , Seung-Hwan Moon
IPC分类号： G09G3/36 , G06F3/038 , G09G5/00
CPC分类号： G09G3/3677 , G09G2300/0426 , G09G2310/0286 , G11C19/184 , G11C19/28
摘要： A gate driving device includes a plurality of stages, a first dummy stage connected to the plurality of stages and a second dummy stage connected to the first dummy stage. Stages of the plurality of stages are cascaded. The first dummy stage includes a first charge unit which receives a first input signal from a previous stage of the plurality of stages and is thereby charged, and a first pull-up transistor which outputs a clock signal when the first charge unit reaches a first charge level. The second dummy stage includes a second charge unit which receives a second input signal from the first dummy stage and is thereby charged, and a second pull-up transistor which outputs the clock signal when the second charge unit reaches a second charge level higher than the first charge level.
摘要翻译：栅极驱动装置包括多个级，连接到多个级的第一虚拟级和连接到第一虚拟级的第二虚拟级。多级的阶段是级联的。第一虚拟级包括第一充电单元，其接收来自多级的前一级的第一输入信号并由此充电;以及第一上拉晶体管，其在第一充电单元达到第一充电时输出时钟信号水平。第二虚拟级包括第二充电单元，其从第一虚拟级接收第二输入信号并由此被充电;以及第二上拉晶体管，当第二充电单元达到比第二充电电平高的第二充电电平时，输出时钟信号第一充电水平。

8. 发明授权

US08305323B2 Display apparatus and method of driving the same 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US08305323B2
公开(公告)日：2012-11-06
申请号：US11960131
申请日：2007-12-19
申请人： Min-Cheol Lee , Byeong-Jae Ahn , Jong-Hwan Lee , Yeon-Kyu Moon , Jong-Hyuk Lee
发明人： Min-Cheol Lee , Byeong-Jae Ahn , Jong-Hwan Lee , Yeon-Kyu Moon , Jong-Hyuk Lee
IPC分类号： G09G3/36 , G09G5/00 , G06F3/038 , H03K23/00 , H03K25/00 , H03K3/00
CPC分类号： G09G3/3674 , G09G2310/0286 , G11C19/182
摘要： A display apparatus includes a gate driver which sequentially outputs a gate signal at a high state in response to a gate control signal and a data driver which converts image data into a data signal in response to a data control signal. The display apparatus further includes a display panel which includes a plurality of gate lines which sequentially receive the gate signal, a plurality of data lines which receive the data signal and a plurality of pixels connected to the gate and data lines and which receive the data signal in response to the gate signal to display an image. The polarity of the data signal is inverted after the gate signal transitions to a low state.
摘要翻译：显示装置包括：栅极驱动器，其响应于栅极控制信号顺序地输出处于高状态的栅极信号;以及数据驱动器，其响应于数据控制信号将图像数据转换为数据信号。显示装置还包括显示面板，其包括顺序地接收栅极信号的多个栅极线，接收数据信号的多个数据线和连接到栅极和数据线的多个像素，并且接收数据信号响应于门信号显示图像。在门信号转换到低电平状态之后，数据信号的极性反转。

9. 发明申请

US20080129717A1 Display panel and display apparatus having the same 有权
标题翻译：显示面板和具有该显示面板的显示装置
公开(公告)号：US20080129717A1
公开(公告)日：2008-06-05
申请号：US11999329
申请日：2007-12-04
申请人： Min-Cheol Lee , Hee-Bum Park , Yong-Soon Lee , Seung-Soo Baek , Sang-jin Jeon
发明人： Min-Cheol Lee , Hee-Bum Park , Yong-Soon Lee , Seung-Soo Baek , Sang-jin Jeon
IPC分类号： G06F3/038
CPC分类号： G09G3/3611 , G09G3/3677 , G09G2320/0223
摘要： In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.
摘要翻译：在具有显示面板的显示面板和显示装置中，显示面板包括阵列和相对的基板。阵列基板包括显示器和外围区域。栅极和源极线形成在显示区域中。在周边区域中形成栅极驱动部分和第一和第二时钟线。栅极驱动部分将栅极信号输出到栅极线。第一和第二时钟线分别将第一和第二时钟信号发送到门驱动部分。相对的衬底与阵列衬底组合并且包括公共电极层。公共电极层具有图案化以暴露第一和第二时钟线的开口部分。第一和第二时钟线的暴露部分具有基本上相同的面积。因此，可以使门信号的延迟最小化并且可以防止门信号的失真。

10. 发明申请

US20070296662A1 GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：闸门驱动电路和显示装置
公开(公告)号：US20070296662A1
公开(公告)日：2007-12-27
申请号：US11763144
申请日：2007-06-14
申请人： Min-Cheol Lee , Seung-Hwan Moon
发明人： Min-Cheol Lee , Seung-Hwan Moon
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G2310/0286
摘要： In a gate driving circuit and a display apparatus, the gate driving circuit comprises a plurality of stages. At least one of the stages comprises a pull-up section responsive to a first node signal; a pull-down section responsive to a second input signal; a discharging section discharging the first node signal in response to the second input signal; a first holding section responsive to the first clock signal, maintaining the first node signal at the off-voltage; and a second holding section responsive to the second clock signal, maintaining the first node signal at the off-voltage. The second holding section has a greater transistor width-to-length ratio than the first holding section. Therefore, an abnormal gate-on signal is less likely to occur, reducing driving defects of the display apparatus.
摘要翻译：在栅极驱动电路和显示装置中，栅极驱动电路包括多个级。至少一个级包括响应于第一节点信号的上拉部分; 响应于第二输入信号的下拉部分; 放电部分，响应于所述第二输入信号而放电所述第一节点信号; 响应于所述第一时钟信号的第一保持部分，将所述第一节点信号保持在所述截止电压; 以及响应于第二时钟信号的第二保持部分，将第一节点信号保持在截止电压。第二保持部具有比第一保持部更大的晶体管宽度比。因此，不太可能发生异常的接通信号，减少了显示装置的驱动缺陷。

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