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1. 发明授权

US10872577B2 Shift register, circuit and driving method thereof, gate drive circuit and display device 有权
公开(公告)号：US10872577B2
公开(公告)日：2020-12-22
申请号：US15753238
申请日：2017-08-25
申请人： BOE TECHNOLOGY GROUP CO., LTD. , ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
发明人： Jun Fan
IPC分类号： G09G3/36 , G09G3/3266 , G11C7/10 , G11C19/18 , G11C19/28
CPC分类号： G09G3/3677 , G09G3/3266 , G11C7/1036 , G11C19/182 , G11C19/28 , G09G2310/0283 , G09G2310/0286
摘要： A shift register circuit is disclosed that includes an initialization circuit, a first node control circuit, a second node control circuit, and an output circuit. The initialization circuit is configured to set a first node to an inactive potential in response to an initialization pulse from an initialization terminal being active. The initialization pulse is immediately prior to an input pulse applied to an input terminal.

2. 发明授权

US08305323B2 Display apparatus and method of driving the same 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US08305323B2
公开(公告)日：2012-11-06
申请号：US11960131
申请日：2007-12-19
申请人： Min-Cheol Lee , Byeong-Jae Ahn , Jong-Hwan Lee , Yeon-Kyu Moon , Jong-Hyuk Lee
发明人： Min-Cheol Lee , Byeong-Jae Ahn , Jong-Hwan Lee , Yeon-Kyu Moon , Jong-Hyuk Lee
IPC分类号： G09G3/36 , G09G5/00 , G06F3/038 , H03K23/00 , H03K25/00 , H03K3/00
CPC分类号： G09G3/3674 , G09G2310/0286 , G11C19/182
摘要： A display apparatus includes a gate driver which sequentially outputs a gate signal at a high state in response to a gate control signal and a data driver which converts image data into a data signal in response to a data control signal. The display apparatus further includes a display panel which includes a plurality of gate lines which sequentially receive the gate signal, a plurality of data lines which receive the data signal and a plurality of pixels connected to the gate and data lines and which receive the data signal in response to the gate signal to display an image. The polarity of the data signal is inverted after the gate signal transitions to a low state.
摘要翻译：显示装置包括：栅极驱动器，其响应于栅极控制信号顺序地输出处于高状态的栅极信号;以及数据驱动器，其响应于数据控制信号将图像数据转换为数据信号。显示装置还包括显示面板，其包括顺序地接收栅极信号的多个栅极线，接收数据信号的多个数据线和连接到栅极和数据线的多个像素，并且接收数据信号响应于门信号显示图像。在门信号转换到低电平状态之后，数据信号的极性反转。

3. 发明授权

US3665210A Monolithic bipolar convertible static shift register 失效
标题翻译：单声双极可调稳态移位寄存器
公开(公告)号：US3665210A
公开(公告)日：1972-05-23
申请号：US3665210D
申请日：1970-06-30
申请人： IBM
发明人： HO IRVING T , HOWELL PETER E , JEN TEH-SEN
IPC分类号： G11C19/18 , G11C19/28 , G11C11/24 , G11C11/34 , G11C19/00
CPC分类号： G11C19/182 , G11C19/28
摘要： A storage cell suitable for implementation as a monolithic shift register in which a pair of monolithic parasitic capacitors are selectively charged solely in response to periodic non-dc signals to set the digital state of the storage cell. Semiconductor switching means connected between the first and second capacitors is responsive to periodic signals to regenerate the cell for operation in a static mode. Alternatively, a dc circuit prevents loss of cell information during a static mode. The semiconductor switching means is virtually eliminated from the circuit by proper biasing so as to also render the cell operable for use in a dynamic shift register mode.

4. 发明授权

US3289010A Shift register 失效
公开(公告)号：US3289010A
公开(公告)日：1966-11-29
申请号：US32529563
申请日：1963-11-21
申请人： BURROUGHS CORP
发明人： BACON JAMES R , BARNES GEORGE H
IPC分类号： G11C19/18
CPC分类号： G11C19/182

5. 发明授权

US3056045A Electronic switching unit for the construction of information storage devices, counters and the like 失效
标题翻译：用于构建信息存储装置，计数器等的电子开关单元
公开(公告)号：US3056045A
公开(公告)日：1962-09-25
申请号：US77609758
申请日：1958-11-24
申请人： INT STANDARD ELECTRIC CORP
发明人： FRIEDRICH ULRICH
IPC分类号： G06F1/04 , G06F9/32 , G11C11/404 , G11C19/18 , G11C19/28 , H03K3/28 , H03K3/57 , H03K17/60 , H03K19/082 , H03K19/12 , H03K23/00
CPC分类号： G06F9/30 , G06F1/04 , G11C11/404 , G11C19/182 , G11C19/28 , H03K3/28 , H03K3/57 , H03K17/60 , H03K17/601 , H03K19/082 , H03K19/12 , H03K23/002

6. 发明授权

US2922985A Shifting register and storage device therefor 失效
标题翻译：移位寄存器和存储设备
公开(公告)号：US2922985A
公开(公告)日：1960-01-26
申请号：US34050353
申请日：1953-03-05
申请人： IBM
发明人： CRAWFORD DAVID J
IPC分类号： G11C19/00 , G11C19/18 , G11C19/20 , G11C19/28 , H03K17/74
CPC分类号： H03K17/74 , G11C19/00 , G11C19/182 , G11C19/202 , G11C19/28

7. 发明申请

US20180130543A1 ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE 审中-公开
公开(公告)号：US20180130543A1
公开(公告)日：2018-05-10
申请号：US15865268
申请日：2018-01-09
申请人： WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.
发明人： Zaiwen ZHU , Yong YUAN , Feng LU , Qijun YAO , Qitai JI
IPC分类号： G11C27/04 , H01L49/02 , H01L27/12 , G06F3/045 , G06F3/041
CPC分类号： G11C27/04 , G06F3/0416 , G06F3/045 , G06F2203/04105 , G06F2203/04111 , G11C19/182 , G11C19/28 , H01L27/124 , H01L27/1255 , H01L28/20
摘要： Provided are an array substrate, a display panel and a display device, and the array substrate includes: at least one pressure sensor disposed in the non-display region; and the pressure sensor includes a first resistor, a second resistor, a third resistor and a fourth resistor; and a plurality of shift registers disposed in the non-display region, and the first resistor, the second resistor, the third resistor and the fourth resistor are disposed at least one of following positions: inside the shift register, between adjacent two of the plurality of shift registers, at a side of the plurality of shift registers close to the display region, and at a side of the plurality of shift registers away from the display region.

8. 发明申请

US20180108301A1 INTEGRATED GATE DRIVER CIRCUIT 审中-公开
公开(公告)号：US20180108301A1
公开(公告)日：2018-04-19
申请号：US15711706
申请日：2017-09-21
申请人： Apple Inc.
发明人： Chin-Wei LIN , Vasudha GUPTA
IPC分类号： G09G3/3266
CPC分类号： G09G3/3266 , G09G2310/0251 , G09G2310/0286 , G09G2310/08 , G11C19/182 , G11C19/28
摘要： A display device may include a plurality of rows of pixels configured to display image data on a display and a first gate driver circuit. The first gate driver circuit may couple a first voltage source to a first node associated with a first gate of a first switch upon receipt of a start signal or a gate signal from another gate driver circuit and couple a first clock signal to a first gate line via the first switch after a first voltage of the first node exceeds a threshold. The threshold is associated with activating the first switch, such that the first gate line is configured to couple to a first row of the plurality of rows of pixels. The first gate driver circuit may then couple a second voltage source to the first node based on a second clock signal, such that the second voltage source discharges the first node.

9. 发明授权

US4627081A Shift register stage 失效
标题翻译：移位寄存器阶段
公开(公告)号：US4627081A
公开(公告)日：1986-12-02
申请号：US682410
申请日：1984-12-17
申请人： Michael J. Gay
发明人： Michael J. Gay
IPC分类号： G11C19/28 , G11C19/18 , G11C27/00
CPC分类号： G11C19/182
摘要： A shift register stage responsive to a clock signal having first and second phases, the stage having an input and an output node (206 and 228) and comprising: capacitive storage means (208); switch means (202, 210) connected between the capacitive storage means and the input node of the stage and having a control electrode; and amplifier means (230) connected between the capacitive storage means and the output node of the stage, the switch means being conductive and non-conductive respectively during the first and second phases of the clock signal so that the capacitive storage means is charged during the first phase of the clock signal to a voltage representative of the voltage at the input node of the stage, and the amplifier means being operative during at least the second phase of the clock signal so that the amplifier means produces at the output node of the stage a voltage representative of the voltage on the capacitive storage means, wherein the voltage applied to the control electrode of the switch means is offset during the first phase of the clock signal by a first offset value from the voltage on the capacitive storage means and is offset during the second phase of the clock signal by a second offset value from the voltage on the capacitive storage means such that any charge removed from the capacitive storage means due to capacitive coupling effects between the capacitive storage means and the control electrode is independent of the voltage on the capacitive storage means.
摘要翻译：响应于具有第一和第二相位的时钟信号的移位寄存器级，所述级具有输入和输出节点（206和228），并且包括：电容存储装置（208）; 开关装置（202,210），连接在电容存储装置和载物台的输入节点之间，并具有控制电极; 以及连接在电容存储装置和级的输出节点之间的放大器装置（230），开关装置分别在时钟信号的第一和第二相期间导通和不导通，使得电容性存储装置在时钟信号的第一相位信号为表示级的输入节点处的电压的电压，并且放大器装置在时钟信号的至少第二相位期间工作，使得放大器装置在级的输出节点处产生表示电容存储装置上的电压的电压，其中施加到开关装置的控制电极的电压在时钟信号的第一阶段期间偏移来自电容性存储装置上的电压的第一偏移值，并且偏移在时钟信号的第二阶段期间通过电容性存储装置上的电压的第二偏移值，使得从电容器由于电容性存储装置和控制电极之间的电容耦合效应，平衡存储装置与电容性存储装置上的电压无关。

10. 发明授权

US3546490A Multi-stage delay line using capacitor charge transfer 失效
标题翻译：多级延时线使用电容充电转移
公开(公告)号：US3546490A
公开(公告)日：1970-12-08
申请号：US3546490D
申请日：1967-10-17
申请人： PHILIPS CORP
发明人： SANGSTER FREDERIK LEONARD JOHA
IPC分类号： G11C19/18 , G11C27/00 , G11C27/04 , H01L27/105 , H03H11/26 , H03K17/60 , H03K17/615 , H03K5/159 , H03K17/28
CPC分类号： G11C19/182 , G11C19/186 , G11C27/00 , G11C27/04 , H01L27/1055 , H03H11/265 , H03K17/60 , H03K17/615

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