会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明申请
    • Method of manufacturing non-volatile DRAM
    • 制造非易失性DRAM的方法
    • US20050170586A1
    • 2005-08-04
    • US10820189
    • 2004-04-06
    • Kyu Choi
    • Kyu Choi
    • G11C11/34G11C11/405G11C14/00G11C16/04H01L21/8239H01L21/8242H01L27/105H01L27/108
    • G11C16/0425G11C11/405G11C14/00G11C14/0018H01L27/105H01L27/1052H01L27/108H01L27/10894
    • A method of forming a non-volatile DRAM includes, in part, forming a first polysilicon layer above a first dielectric layer to form a control gate of the non-volatile device disposed in the non-volatile DRAM, forming sidewall spacers adjacent the first polysilicon layer, forming a second polysilicon layer that forms a guiding gate of the non-volatile device disposed in the non-volatile DRAM and a gate of an MOS transistor disposed in the non-volatile DRAM, delivering first implants to the body region to form lightly doped areas in the body region, delivering second implants to the body region to define source and drain regions, forming second sidewall spacers above the body region to define regions receiving lightly dopes implants and to define a conducting region of a capacitor disposed in the non-volatile DRAM.
    • 形成非易失性DRAM的方法部分地包括在第一介电层上形成第一多晶硅层以形成设置在非易失性DRAM中的非易失性器件的控制栅极,形成邻近第一多晶硅的侧壁间隔物 形成第二多晶硅层,其形成设置在非易失性DRAM中的非易失性器件的引导栅极和设置在非易失性DRAM中的MOS晶体管的栅极,将第一植入物递送到身体区域以形成轻微的 在身体区域中的掺杂区域,将第二植入物递送到身体区域以限定源极和漏极区域,在身体区域上方形成第二侧壁间隔,以限定接收轻度掺杂植入物的区域,并且限定设置在非区域中的电容器的导电区域, 易失性DRAM。
    • 4. 发明申请
    • Non-volatile memory device
    • 非易失性存储器件
    • US20060007772A1
    • 2006-01-12
    • US11189548
    • 2005-07-25
    • Kyu Choi
    • Kyu Choi
    • G11C8/02
    • G11C14/00
    • A non-volatile memory device includes a guiding gate that extends along a first portion of the device's channel length and a control gate that extends along a second portion of the device's channel length. The first and second portions of the channel length do not overlap. The guiding gate, which overlays the substrate above the channel region, is insulated from the semiconductor substrate in which the device is formed via an oxide layer. The channel region under the guiding gate has a doping concentration greater than the doping concentration of the substrate. The remaining portion of the channel region has a doping concentration greater than the doping concentration of the substrate but less than the doping concentration of the channel region under the guiding gate. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer.
    • 非易失性存储器件包括沿器件沟道长度的第一部分延伸的引导门和沿设备通道长度的第二部分延伸的控制栅极。 通道长度的第一和第二部分不重叠。 在通道区域上方覆盖衬底的引导栅极与通过氧化物层形成器件的半导体衬底绝缘。 引导栅极下方的沟道区域的掺杂浓度大于衬底的掺杂浓度。 沟道区的剩余部分的掺杂浓度大于衬底的掺杂浓度,但是小于引导栅下的沟道区的掺杂浓度。 也在通道区域上方覆盖衬底的控制栅极通过氧化物 - 氮化物 - 氧化物层与衬底绝缘。
    • 7. 发明申请
    • Non-volatile and static random access memory cells sharing the same bitlines
    • 共享相同位线的非易失性和静态随机存取存储单元
    • US20060193174A1
    • 2006-08-31
    • US11067313
    • 2005-02-25
    • David ChoiEui KwonKyu Choi
    • David ChoiEui KwonKyu Choi
    • G11C11/34G11C14/00
    • G11C14/00
    • A memory cell structure includes non-volatile as well as SRAM memory cells that share the same bitline and operate differentially. The SRAM cell includes first and second MOS transistors that are coupled to the same true and complementary bit lines that the non-volatile memory cells are coupled to. The non-volatile memory cells are erased prior to being programmed. Programming of the non-volatile memory cells may be carried out via hot-electron injection or Fowler-Nordheim tunneling. Data stored in the non-volatile memory cells may be transferred to the SRAM cell. The differential reading and writing of data reduces over-erase of the non-volatile devices.
    • 存储单元结构包括非易失性以及共享相同位线并且差分操作的SRAM存储器单元。 SRAM单元包括耦合到与非易失性存储单元耦合的相同真和互补位线的第一和第二MOS晶体管。 在编程之前擦除非易失性存储单元。 非易失性存储器单元的编程可以通过热电子注入或Fowler-Nordheim隧道进行。 存储在非易失性存储单元中的数据可以被传送到SRAM单元。 差分读取和写入数据减少了非易失性器件的过度擦除。
    • 8. 发明申请
    • Non-volatile memory array
    • 非易失性存储器阵列
    • US20050219913A1
    • 2005-10-06
    • US10819669
    • 2004-04-06
    • Kyu ChoiSheau-suey Li
    • Kyu ChoiSheau-suey Li
    • G11C16/04G11C16/06G11C16/10
    • G11C16/0425G11C16/0466G11C16/10
    • Each non-volatile memory cell of an array of includes a guiding gate extending along a first portion of the cell's channel and a control gate extending along a second portion of the cell's channel. The first and second portions of the channel do not overlap. The guiding gate, which overlays the substrate above the channel, is insulated from the substrate via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer. Each row of the array has a first terminal coupled to the guiding gates, and a second terminal coupled to the control gates of the cells disposed in that row. Each column of the array has a first terminal coupled to the drain regions, and a second terminal coupled to the source regions of the cells disposed in that column.
    • 阵列的每个非易失性存储单元包括沿单元通道的第一部分延伸的引导门和沿着单元通道的第二部分延伸的控制栅。 通道的第一和第二部分不重叠。 引导栅极覆盖通道上方的衬底,通过氧化物层与衬底绝缘。 也在通道区域上方覆盖衬底的控制栅极经由氧化物 - 氮化物 - 氧化物层与衬底绝缘。 阵列的每一列具有耦合到引导栅极的第一端子,以及耦合到设置在该行中的单元的控制栅极的第二端子。 阵列的每列具有耦合到漏极区的第一端子和耦合到设置在该列中的单元的源极区域的第二端子。