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1. 发明申请

US20050219913A1 Non-volatile memory array 审中-公开
标题翻译：非易失性存储器阵列
公开(公告)号：US20050219913A1
公开(公告)日：2005-10-06
申请号：US10819669
申请日：2004-04-06
申请人： Kyu Choi , Sheau-suey Li
发明人： Kyu Choi , Sheau-suey Li
IPC分类号： G11C16/04 , G11C16/06 , G11C16/10
CPC分类号： G11C16/0425 , G11C16/0466 , G11C16/10
摘要： Each non-volatile memory cell of an array of includes a guiding gate extending along a first portion of the cell's channel and a control gate extending along a second portion of the cell's channel. The first and second portions of the channel do not overlap. The guiding gate, which overlays the substrate above the channel, is insulated from the substrate via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer. Each row of the array has a first terminal coupled to the guiding gates, and a second terminal coupled to the control gates of the cells disposed in that row. Each column of the array has a first terminal coupled to the drain regions, and a second terminal coupled to the source regions of the cells disposed in that column.
摘要翻译：阵列的每个非易失性存储单元包括沿单元通道的第一部分延伸的引导门和沿着单元通道的第二部分延伸的控制栅。通道的第一和第二部分不重叠。引导栅极覆盖通道上方的衬底，通过氧化物层与衬底绝缘。也在通道区域上方覆盖衬底的控制栅极经由氧化物 - 氮化物 - 氧化物层与衬底绝缘。阵列的每一列具有耦合到引导栅极的第一端子，以及耦合到设置在该行中的单元的控制栅极的第二端子。阵列的每列具有耦合到漏极区的第一端子和耦合到设置在该列中的单元的源极区域的第二端子。

2. 发明授权

US06954377B2 Non-volatile differential dynamic random access memory 失效
标题翻译：非易失性差分动态随机存取存储器
公开(公告)号：US06954377B2
公开(公告)日：2005-10-11
申请号：US10394496
申请日：2003-03-19
申请人： Kyu Hyun Choi , Sheau-suey Li
发明人： Kyu Hyun Choi , Sheau-suey Li
IPC分类号： G11C14/00
CPC分类号： G11C14/00
摘要： In accordance with the present invention, a memory cell includes a pair of non-volatile devices and a pair of DRAM cells each associated with a different one of the non-volatile devices. Each DRAM cell further includes an MOS transistor a capacitor. The DRAM cells and their associated non-volatile devices operate differentially and when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the DRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.
摘要翻译：根据本发明，存储单元包括一对非易失性器件和一对DRAM单元，每个DRAM单元与不同的非易失性器件相关联。每个DRAM单元还包括一个MOS晶体管，一个电容器。 DRAM单元及其相关的非易失性器件在编程时存储和供应补充数据时工作差异。非易失性器件在编程之前被擦除。非易失性器件的编程可以通过热电子注入或Fowler-Nordheim隧道进行。当发生电源故障时，存储在DRAM中的数据被加载到非易失性设备中。在电源恢复之后，存储在非易失性设备中的数据在DRAM单元中恢复。数据的差分读取和拧紧减少了非易失性器件的过擦除。

3. 发明授权

US06806148B1 Method of manufacturing non-volatile memory device 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US06806148B1
公开(公告)日：2004-10-19
申请号：US10447715
申请日：2003-05-28
申请人： Kyu Hyun Choi , Sheau-suey Li
发明人： Kyu Hyun Choi , Sheau-suey Li
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11546
摘要： A method of forming an integrated circuit, includes, in part: forming trench isolation in a semiconductor substrate, forming a first well between the trench isolation, forming a second well above the first well, forming a first oxide layer above a first portion of the second well, forming a first dielectric layer above the first oxide layer, forming a first polysilicon gate layer above the first dielectric layer, forming a second dielectric layer above the first polysilicon layer, forming a first spacer above the body region and adjacent the first polysilicon layer, forming a second oxide layer above a second portion of the second well not covered by the first spacer, forming a second polysilicon gate layer above the second oxide layer, the first spacer and a portion of the second dielectric layer, and forming a second spacer to define source and drain regions.
摘要翻译：形成集成电路的方法部分包括：在半导体衬底中形成沟槽隔离，在沟槽隔离之间形成第一阱，在第一阱之上形成第二阱，在第一阱的第一部分上方形成第一氧化物层在所述第一氧化物层的上方形成第一电介质层，在所述第一电介质层的上方形成第一多晶硅栅极层，在所述第一多晶硅层的上方形成第二电介质层，在所述主体区域的上方形成与所述第一多晶硅在第二阱的不被第一间隔物覆盖的第二部分上方形成第二氧化物层，在第二氧化物层上方形成第二多晶硅栅极层，第一间隔物和第二电介质层的一部分，并形成第二氧化物层间隔物以限定源区和漏区。

4. 发明授权

US07232717B1 Method of manufacturing non-volatile DRAM 失效
标题翻译：制造非易失性DRAM的方法
公开(公告)号：US07232717B1
公开(公告)日：2007-06-19
申请号：US10447675
申请日：2003-05-28
申请人： Kyu Hyun Choi , Sheau-suey Li
发明人： Kyu Hyun Choi , Sheau-suey Li
IPC分类号： H01L21/8244
CPC分类号： H01L27/115 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/11521
摘要： A method of forming a non-volatile DRAM includes, in part: forming p-well and an n-well between two trench isolation regions formed in a semiconductor substrate, forming a polysilicon control gate of the non-volatile device disposed in the non-volatile DRAM, forming a first oxide spacer above portions of the body region and adjacent said first control gate, forming gate oxide layers of varying thicknesses above the body region, forming the guiding gate of the non-volatile device and the gate of an associated passgate transistor, forming LDD implant regions of the non-volatile device and the associated pass-gate transistor, forming source/drain regions of the non-volatile device and the associated pass-gate transistor, depositing a dielectric layer over the polysilicon guiding gate of the non-volatile device and the polysilicon gate of the associated passgate transistor, forming polysilicon landing pads, and forming polysilicon vertical walls defining capacitor plates of the non-volatile DRAM capacitor.
摘要翻译：形成非挥发性DRAM的方法部分包括：形成在半导体衬底中的两个沟槽隔离区之间形成p阱和n阱，形成设置在非易失性DRAM中的非易失性器件的多晶硅控制栅极，在本体区域的部分和邻近所述第一控制栅极之上形成第一氧化物隔离层，在体区上方形成不同厚度的栅极氧化物层，形成非易失性器件的引导栅极和相关联的栅极晶体管，形成非易失性器件的LDD注入区和相关联的栅极晶体管，形成非易失性器件的源极/漏极区域和相关联的栅极 - 晶体管，在介电层的多晶硅引导栅极上沉积介电层非易失性器件和相关联的闸门晶体管的多晶硅栅极，形成多晶硅着陆焊盘，以及形成限定非挥发物的电容器板的多晶硅垂直壁 e DRAM电容。

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