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1. 发明申请

US20080157200A1 STRESS LINER SURROUNDED FACETLESS EMBEDDED STRESSOR MOSFET 审中-公开
标题翻译：应力衬里无缝嵌入式应力MOSFET
公开(公告)号：US20080157200A1
公开(公告)日：2008-07-03
申请号：US11616730
申请日：2006-12-27
申请人： Byeong Y. Kim , Shahid A. Butt , Xiaomeng Chen , Shwu-Jen J. Jeng , Hasan M. Nayfeh , Deepal Wehella-Gamage
发明人： Byeong Y. Kim , Shahid A. Butt , Xiaomeng Chen , Shwu-Jen J. Jeng , Hasan M. Nayfeh , Deepal Wehella-Gamage
IPC分类号： H01L29/78
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/201 , H01L29/221 , H01L29/66628 , H01L29/66772 , H01L29/78 , H01L29/7846 , H01L29/7848 , H01L29/78684
摘要： The present invention provides an STI bounded transistor structure having enhanced performance which is not diminished due to embedded stressor facets that can be present at the edge of the source/drain regions that contacts an embedded stressor material. Considering that the facet in the prior art is due to an STI divot formed during several necessary wet etching processes, the MOSFET source/drain edge of the inventive structure is surrounded by a liner to prevent facet growth during the epitaxial growth of the stressor material. As such, a part of the semiconductor substrate edge is preserved. The liner employed in the present invention is a stress engineering material such as, for example, silicon nitride.
摘要翻译：本发明提供了一种具有增强性能的STI界限晶体管结构，其由于可能存在于接触嵌入的应力源材料的源极/漏极区域的边缘处的嵌入的应力小面而不会减小。考虑到现有技术中的方面是由于在几个必要的湿蚀刻工艺期间形成的STI纹路，本发明结构的MOSFET源极/漏极边缘被衬垫围绕，以防止在应力源材料的外延生长期间的面生长。因此，半导体衬底边缘的一部分被保留。本发明中使用的衬垫是应力工程材料，例如氮化硅。

2. 发明授权

US08754446B2 Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material 有权
标题翻译：半导体结构具有由保护性阻挡材料包围的底切栅氧化物栅叠层
公开(公告)号：US08754446B2
公开(公告)日：2014-06-17
申请号：US11468403
申请日：2006-08-30
申请人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
发明人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.
摘要翻译：本发明涉及形成具有密封栅极氧化物层的结构的结构和方法。该结构包括在衬底上形成的栅极氧化层和形成在栅极氧化物层上的栅极。该结构还包括栅极的材料邻接壁并形成在栅极下方的底切之下，以保护由底切露出的栅极氧化物层的区域。源极和漏极区域通过材料与栅极隔离。

3. 发明授权

US07491623B2 Method of making a semiconductor structure 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US07491623B2
公开(公告)日：2009-02-17
申请号：US11841018
申请日：2007-08-20
申请人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
发明人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
IPC分类号： H01L21/76
CPC分类号： H01L29/7848 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.
摘要翻译：本发明涉及形成具有密封栅极氧化物层的结构的结构和方法。该结构包括在衬底上形成的栅极氧化层和形成在栅极氧化物层上的栅极。该结构还包括栅极的材料邻接壁并形成在栅极下方的底切之下，以保护由底切露出的栅极氧化物层的区域。源极和漏极区域通过材料与栅极隔离。

4. 发明申请

US20080121931A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20080121931A1
公开(公告)日：2008-05-29
申请号：US11468403
申请日：2006-08-30
申请人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
发明人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.
摘要翻译：本发明涉及形成具有密封栅极氧化物层的结构的结构和方法。该结构包括在衬底上形成的栅极氧化层和形成在栅极氧化物层上的栅极。该结构还包括栅极的材料邻接壁并形成在栅极下方的底切之下，以保护由底切露出的栅极氧化物层的区域。源极和漏极区域通过材料与栅极隔离。

5. 发明申请

US20090321794A1 CMOS DEVICES INCORPORATING HYBRID ORIENTATION TECHNOLOGY (HOT) WITH EMBEDDED CONNECTORS 有权
标题翻译：嵌入式连接器的混合定向技术（HOT）的CMOS器件
公开(公告)号：US20090321794A1
公开(公告)日：2009-12-31
申请号：US12555350
申请日：2009-09-08
申请人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
发明人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207
摘要： The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
摘要翻译：本发明涉及具有混合通道取向并由嵌入在半导体衬底中的导电连接器连接的诸如n-FET和p-FET的互补器件。具体地，半导体衬底具有至少具有不同表面晶取向（即混合取向）的第一和第二器件区域。 n-FET形成在第一和第二器件区域中的一个处，并且p-FET形成在第一和第二器件区域中的另一个处。 n-FET和p-FET通过位于第一和第二器件区域之间的导电连接器电连接并嵌入在半导体衬底中。优选地，介电隔离件首先设置在第一和第二器件区域之间并且凹入以在它们之间形成间隙。然后将导电连接器形成在凹入的电介质间隔物上方的间隙中。

6. 发明申请

US20080224255A1 SUBGROUND RULE STI FILL FOR HOT STRUCTURE 审中-公开
公开(公告)号：US20080224255A1
公开(公告)日：2008-09-18
申请号：US12111238
申请日：2008-04-29
申请人： Byeong Y. Kim , Munir D. Naeem , Frank D. Tamweber , Xiaomeng Chen
发明人： Byeong Y. Kim , Munir D. Naeem , Frank D. Tamweber , Xiaomeng Chen
IPC分类号： H01L29/00
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.

7. 发明申请

US20080083952A1 SEMICONDUCTOR STRUCTURES INCLUDING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND METHODS FOR FABRICATION THEREOF 失效
标题翻译：包括多个晶体学方位的半导体结构及其制造方法
公开(公告)号：US20080083952A1
公开(公告)日：2008-04-10
申请号：US11538963
申请日：2006-10-05
申请人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
发明人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.
摘要翻译：半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。半导体衬底暴露在绝缘体内半导体结构内的孔内。外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。

8. 发明授权

US07494918B2 Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof 失效
标题翻译：包括多个晶体取向的半导体结构及其制造方法
公开(公告)号：US07494918B2
公开(公告)日：2009-02-24
申请号：US11538963
申请日：2006-10-05
申请人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
发明人： Byeong Y. Kim , Xiaomeng Chen , Judson R. Holt , Christopher D. Sheraw , Linda Black , Igor Peidous
IPC分类号： H01L21/4763 , H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.
摘要翻译：半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。半导体衬底暴露在绝缘体内半导体结构内的孔内。外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。

9. 发明授权

US07595232B2 CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors 失效
标题翻译：采用嵌入式连接器的混合定向技术（HOT）的CMOS器件
公开(公告)号：US07595232B2
公开(公告)日：2009-09-29
申请号：US11470819
申请日：2006-09-07
申请人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
发明人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207
摘要： The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
摘要翻译：本发明涉及具有混合通道取向并由嵌入在半导体衬底中的导电连接器连接的诸如n-FET和p-FET的互补器件。具体地，半导体衬底具有至少具有不同表面晶取向（即混合取向）的第一和第二器件区域。 n-FET形成在第一和第二器件区域中的一个处，并且p-FET形成在第一和第二器件区域中的另一个处。 n-FET和p-FET通过位于第一和第二器件区域之间的导电连接器电连接并嵌入在半导体衬底中。优选地，介电隔离件首先设置在第一和第二器件区域之间并且凹入以在它们之间形成间隙。然后将导电连接器形成在凹入的电介质间隔物上方的间隙中。

10. 发明申请

US20120292668A1 CMOS DEVICES INCORPORATING HYBRID ORIENTATION TECHNOLOGY (HOT) WITH EMBEDDED CONNECTORS 有权
标题翻译：嵌入式连接器的混合定向技术（HOT）的CMOS器件
公开(公告)号：US20120292668A1
公开(公告)日：2012-11-22
申请号：US13559877
申请日：2012-07-27
申请人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
发明人： Byeong Y. Kim , Xiaomeng Chen , Yoichi Otani
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207
摘要： The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
摘要翻译：本发明涉及具有混合通道取向并由嵌入在半导体衬底中的导电连接器连接的诸如n-FET和p-FET的互补器件。具体地，半导体衬底具有至少具有不同表面晶取向（即混合取向）的第一和第二器件区域。 n-FET形成在第一和第二器件区域中的一个处，并且p-FET形成在第一和第二器件区域中的另一个处。 n-FET和p-FET通过位于第一和第二器件区域之间的导电连接器电连接并嵌入在半导体衬底中。优选地，介电隔离件首先设置在第一和第二器件区域之间并且凹入以在它们之间形成间隙。然后将导电连接器形成在凹入的电介质间隔物上方的间隙中。

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