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1. 发明授权

US08587458B2 Unpacking a variable number of data bits 有权
标题翻译：打开一个可变数量的数据位
公开(公告)号：US08587458B2
公开(公告)日：2013-11-19
申请号：US13313833
申请日：2011-12-07
申请人： Bulent Abali , Bartholomew Blaner , John J. Reilly
发明人： Bulent Abali , Bartholomew Blaner , John J. Reilly
IPC分类号： H03M7/00
CPC分类号： H03M7/4031 , H03M7/6029
摘要： Unpacking a variable number of data bits is provided. A structure includes an input port operable to receive one or more input data units including a plurality of packed bits of data, each of the one or more input data units including a header and a payload, the header including a predetermined number of bits and identifying a format of the payload and a length of the payload, and the payload including a variable number of bits. The structure further includes a circuit operable to identify and unpack the one or more input data units based on the header and the payload of each of the one or more input data units. The structure further includes an output port operable to transmit one or more output data units including the unpacked one or more input data units, once per clock cycle.
摘要翻译：提供了可变数量的数据位开箱。一种结构包括：输入端口，用于接收一个或多个输入数据单元，所述输入数据单元包括数据的多个压缩位，所述一个或多个输入数据单元中的每一个包括报头和有效载荷，所述报头包括预定数量的位和识别有效载荷的格式和有效载荷的长度，并且有效载荷包括可变位数。该结构还包括可操作以基于一个或多个输入数据单元中的每一个的标题和有效载荷来识别和解包一个或多个输入数据单元的电路。该结构还包括输出端口，其可操作以每时钟周期一次传送包括未封装的一个或多个输入数据单元的一个或多个输出数据单元。

2. 发明授权

US08775776B2 Hash table using hash table banks 失效
标题翻译：哈希表使用哈希表银行
公开(公告)号：US08775776B2
公开(公告)日：2014-07-08
申请号：US13352410
申请日：2012-01-18
申请人： Bulent Abali , John J. Reilly
发明人： Bulent Abali , John J. Reilly
IPC分类号： G06F12/00
CPC分类号： G06F17/30097
摘要： A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).
摘要翻译：哈希表方法和结构包括接收多个访问存储设备的访问请求的处理器。处理器对访问请求执行多个哈希处理，以为每个访问请求生成第一数量的地址。这样的地址在一个完整的地址范围内。哈希表库可操作地连接到处理器。哈希表库形成存储设备。每个散列表组具有多个输入端口。具体地说，每个哈希表组对于每个访问请求具有比第一数量的地址少的输入端口。处理器向散列表组提供地址，并且每个散列表存储体存储对应于在完整地址范围内的不同有限范围的地址的指针（每个不同的有限的地址范围小于全地址范围）。

3. 发明申请

US20130185537A1 HASH TABLE USING HASH TABLE BANKS 失效
公开(公告)号：US20130185537A1
公开(公告)日：2013-07-18
申请号：US13352410
申请日：2012-01-18
申请人： Bulent Abali , John J. Reilly
发明人： Bulent Abali , John J. Reilly
IPC分类号： G06F12/08
CPC分类号： G06F17/30097
摘要： A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).
摘要翻译：哈希表方法和结构包括接收多个访问存储设备的访问请求的处理器。处理器对访问请求执行多个哈希处理，以为每个访问请求生成第一数量的地址。这样的地址在一个完整的地址范围内。哈希表库可操作地连接到处理器。哈希表库形成存储设备。每个散列表组具有多个输入端口。具体地说，每个哈希表组对于每个访问请求具有比第一数量的地址少的输入端口。处理器向散列表组提供地址，并且每个散列表存储体存储对应于在完整地址范围内的不同有限范围的地址的指针（每个不同的有限的地址范围小于全地址范围）。

4. 发明申请

US20140185753A1 VEHICLE-MOUNTED CARGO INSPECTION SYSTEM 审中-公开
标题翻译：车辆安装货物检查系统
公开(公告)号：US20140185753A1
公开(公告)日：2014-07-03
申请号：US13538241
申请日：2012-06-29
申请人： Sarfraz Azmi , Jasper Bogosian, JR. , John J. Reilly , Randy Barnby
发明人： Sarfraz Azmi , Jasper Bogosian, JR. , John J. Reilly , Randy Barnby
IPC分类号： G01V5/00
CPC分类号： G01V5/005 , G01V5/0016
摘要： Some embodiments of the invention provide a mobile cargo inspection system mounted on a vehicle chassis type which does not include rails that extend from near the front of the vehicle to near the back. As such, detection components may be placed between the front and rear axles of the vehicle without penetrating radiation having to pass through a chassis rail before reaching the cargo to be inspected. As a result, the weight of the vehicle-mounted cargo inspection system may be more evenly distributed from the front of the vehicle to the back, and from one side of the vehicle to the other, thus making the system easier to operate, safer, and less costly to maintain than conventional systems.
摘要翻译：本发明的一些实施例提供了一种安装在车辆底盘类型上的移动货物检查系统，其不包括从车辆前部附近延伸到靠近后部的轨道。因此，检测部件可以放置在车辆的前轴和后轴之间，而不会在到达要检查的货物之前必须穿过底盘轨道的穿透辐射。结果，车载货物检查系统的重量可以从车辆的前方更均匀地分布到后部，并且从车辆的一侧到另一侧，从而使得系统更容易操作，更安全，并且比常规系统维护成本更低。

5. 发明申请

US20090222772A1 Power Gating Logic Cones 有权
标题翻译：电源门控逻辑锥
公开(公告)号：US20090222772A1
公开(公告)日：2009-09-03
申请号：US12038845
申请日：2008-02-28
申请人： Steven E Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
发明人： Steven E Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： Power gating logic cones is described. In one embodiment a method includes synthesizing logic for an integrated circuit (IC) design; identifying low switching nodes within the logic that switch less than a threshold; determining a potential power gating cone (PGC) based on the identified low switching nodes; determining a power gating logic expression for the potential PGC that includes a minimum set of inputs to the potential PGC that are least switching; determining whether energy savings using the power gating logic expression meets a criteria; and accepting the potential PGC in response to meeting the criteria.
摘要翻译：描述了电源门控逻辑锥。在一个实施例中，一种方法包括用于集成电路（IC）设计的合成逻辑; 识别切换小于阈值的逻辑内的低交换节点; 基于所识别的低交换节点确定潜在功率门控锥（PGC）; 确定潜在PGC的功率选通逻辑表达式，其包括对最不切换的电位PGC的最小输入集合; 确定使用电源门控逻辑表达式的节能是否符合标准; 并接受潜在的PGC以满足标准。

6. 发明授权

US5459843A RISC-type pipeline processor having N slower execution units operating in parallel interleaved and phase offset manner with a faster fetch unit and a faster decoder 失效
标题翻译：具有N个较慢执行单元的RISC型流水线处理器以并行交错和相位偏移方式工作，具有更快的提取单元和更快的解码器
公开(公告)号：US5459843A
公开(公告)日：1995-10-17
申请号：US282412
申请日：1994-07-28
申请人： Gordon T. Davis , Sebastian T. Ventrone , John J. Reilly , Baiju D. Mandalia , Michael G. Holung , William R. Robinson, Jr.
发明人： Gordon T. Davis , Sebastian T. Ventrone , John J. Reilly , Baiju D. Mandalia , Michael G. Holung , William R. Robinson, Jr.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/3851
摘要： A pipelined, RISC-type processor operated in parallel mode and its associated processing methods for separately handling instructions from multiple program instruction sets. The pipelined processor includes an instruction fetch unit, an instruction decode unit and n execution units. Each execution unit operates at substantially the same process cycle time, while the speed of operation of the instruction fetch unit and instruction decode unit is at least n times the cycle time of the execution units such that each phase of the pipeline separately processes n instructions substantially within one machine cycle. Timing and control circuitry is coupled to each of the principle elemental units for controlling the timing and sequence of operations on instructions.
摘要翻译：以并行模式运行的流水线RISC型处理器及其相关处理方法，用于分别处理来自多个程序指令集的指令。流水线处理器包括指令提取单元，指令解码单元和n个执行单元。每个执行单元以基本上相同的处理周期时间操作，而指令获取单元和指令解码单元的操作速度至少为执行单元的周期时间的n倍，使得流水线的每个相分别基本上处理n个指令在一个机器周期内。定时和控制电路耦合到每个主要元件单元，用于控制指令上的操作的时序和顺序。

7. 发明授权

US08868584B2 Compression pattern matching 有权
标题翻译：压缩模式匹配
公开(公告)号：US08868584B2
公开(公告)日：2014-10-21
申请号：US13350016
申请日：2012-01-13
申请人： John J. Reilly
发明人： John J. Reilly
IPC分类号： G06F17/30
CPC分类号： H03M7/4031 , H03M7/3086
摘要： Systems and methods are provided for data comparisons in a compression algorithm to optimize the compression of data. An exemplary method includes receiving input data. The method further includes generating a hash table address for the input data. The method further includes obtaining a pointer associated with the hash table address. The method further includes reading a data library with the pointer to obtain an associated piece of historical data. The method further includes comparing the historical data to the input data to determine a match.
摘要翻译：提供了系统和方法用于压缩算法中的数据比较，以优化数据的压缩。示例性方法包括接收输入数据。该方法还包括为输入数据生成哈希表地址。该方法还包括获得与散列表地址相关联的指针。该方法还包括用指针读取数据库以获得相关联的一段历史数据。该方法还包括将历史数据与输入数据进行比较以确定匹配。

8. 发明申请

US20090322873A1 SURVEILLANCE SYSTEMS AND METHODS WITH SUBJECT-RELATED SCREENING 有权
标题翻译：监督系统和方法与主题相关的筛选
公开(公告)号：US20090322873A1
公开(公告)日：2009-12-31
申请号：US11740133
申请日：2007-04-25
申请人： John J. Reilly , Thomas E. Breen , Paul J. Hurd , Michael J. Lanzaro , Maya M. Radzinski , Thomas W. Grudkowski , Edward E. Bromberg , Joseph Carter
发明人： John J. Reilly , Thomas E. Breen , Paul J. Hurd , Michael J. Lanzaro , Maya M. Radzinski , Thomas W. Grudkowski , Edward E. Bromberg , Joseph Carter
IPC分类号： H04N7/18
CPC分类号： G01S13/04 , G01S7/411 , G01S13/887 , G01S13/89 , G01V11/00 , G06K9/00771 , G06K9/033 , G06K2209/09
摘要： A surveillance system is disclosed. In some embodiments, the surveillance system may include at least one controller configured to receive information data from at least one upstream information source and to control operation of at least one controllable downstream information source based, at least in part, on the information data.A surveillance method also is disclosed. In some embodiments, the method may include analyzing screening data, obtaining information data, and reanalyzing the screening data based, at least in part, on the obtained information data.
摘要翻译：公开了一种监视系统。在一些实施例中，监视系统可以包括至少一个控制器，其被配置为从至少一个上游信息源接收信息数据，并且至少部分地基于信息数据来控制至少一个可控下游信息源的操作。还公开了一种监视方法。在一些实施例中，该方法可以包括至少部分地基于获得的信息数据来分析筛选数据，获得信息数据和重新分析筛选数据。

9. 发明授权

US07561664B2 Increased throughput inspection station 失效
标题翻译：增加吞吐量检测站
公开(公告)号：US07561664B2
公开(公告)日：2009-07-14
申请号：US11545166
申请日：2006-10-10
申请人： Arkady Mikhail Teslyar , Joseph Parisi , John J. Reilly
发明人： Arkady Mikhail Teslyar , Joseph Parisi , John J. Reilly
IPC分类号： G01N23/04
CPC分类号： G01N23/04 , B64F1/368 , B65G13/00 , G01V5/0008
摘要： A method and apparatus for inspecting items for the presence of contraband. Trays may be used to hold items as they move through an inspection station. After use, the trays may be mechanically conveyed back to an entry region of the inspection station so that the trays may be used to move other items. Mechanically conveying the trays may enable increased throughput for inspection stations. A tray return may be constructed from multiple modules positioned to the side of an inspection machine. In use at an airport or other similar facility, the tray return may face a passenger use area at an inspection station. Passengers exiting the inspection station may place trays in the tray return. Passengers entering the inspection station may remove a tray from an end of the tray return at an entrance of the inspection station.
摘要翻译：检查违禁品存在的物品的方法和装置。托盘可以用于在移动通过检查站时保持物品。使用后，托盘可以被机械地输送回到检查站的入口区域，使得托盘可以用于移动其他物品。机械地输送托盘可以提高检查站的生产量。托盘返回可以由定位在检查机侧面的多个模块构成。在机场或其他类似设施使用时，托盘返回可能面向检查站的乘客使用区域。离开检验站的乘客可将托盘放在托盘返回处。进入检查站的乘客可以从检查站入口处的托盘返回端取出托盘。

10. 发明授权

US07539968B2 Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints 失效
标题翻译：集成电路设计的迭代合成，用于实现电源关闭，同时保持现有的设计约束
公开(公告)号：US07539968B2
公开(公告)日：2009-05-26
申请号：US11759332
申请日：2007-06-07
申请人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
发明人： Steven E. Charlebois , Paul D. Kartschoke , John J. Reilly , Manikandan Viswanath
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： An approach that iteratively synthesizes an integrated circuit design to attain power closure is described. In one embodiment, the integrated circuit design is initially synthesized to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated.
摘要翻译：描述了迭代地合成集成电路设计以获得功率闭合的方法。在一个实施例中，集成电路设计最初被合成以满足定时和功率约束。将初始合成的结果反馈到合成过程中，其中电路设计中的特定节点被定位以满足定时和功率约束。电路设计中的选定节点以迭代的方式进行处理，直到确定所有选定的节点都经历了满足定时和功率约束的评估。一旦所有选定的节点都进行了满足定时和功率约束的评估，则产生表示电路设计的最终网表。

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