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1. 发明授权

US08587458B2 Unpacking a variable number of data bits 有权
标题翻译：打开一个可变数量的数据位
公开(公告)号：US08587458B2
公开(公告)日：2013-11-19
申请号：US13313833
申请日：2011-12-07
申请人： Bulent Abali , Bartholomew Blaner , John J. Reilly
发明人： Bulent Abali , Bartholomew Blaner , John J. Reilly
IPC分类号： H03M7/00
CPC分类号： H03M7/4031 , H03M7/6029
摘要： Unpacking a variable number of data bits is provided. A structure includes an input port operable to receive one or more input data units including a plurality of packed bits of data, each of the one or more input data units including a header and a payload, the header including a predetermined number of bits and identifying a format of the payload and a length of the payload, and the payload including a variable number of bits. The structure further includes a circuit operable to identify and unpack the one or more input data units based on the header and the payload of each of the one or more input data units. The structure further includes an output port operable to transmit one or more output data units including the unpacked one or more input data units, once per clock cycle.
摘要翻译：提供了可变数量的数据位开箱。一种结构包括：输入端口，用于接收一个或多个输入数据单元，所述输入数据单元包括数据的多个压缩位，所述一个或多个输入数据单元中的每一个包括报头和有效载荷，所述报头包括预定数量的位和识别有效载荷的格式和有效载荷的长度，并且有效载荷包括可变位数。该结构还包括可操作以基于一个或多个输入数据单元中的每一个的标题和有效载荷来识别和解包一个或多个输入数据单元的电路。该结构还包括输出端口，其可操作以每时钟周期一次传送包括未封装的一个或多个输入数据单元的一个或多个输出数据单元。

2. 发明授权

US09448846B2 Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines 有权
标题翻译：用于将作业调度到多个硬件加速引擎的动态配置的硬件队列
公开(公告)号：US09448846B2
公开(公告)日：2016-09-20
申请号：US13323914
申请日：2011-12-13
申请人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, Jr. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
发明人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, Jr. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
IPC分类号： G06F9/46 , G06F9/50 , G06F9/48
CPC分类号： G06F9/5038 , G06F9/4843 , G06F9/5027 , G06F2209/5021
摘要： A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.
摘要翻译：一种具有多个处理资源的计算机系统，包括用于向多个硬件加速器调度和调度处理作业的子系统，所述子系统还包括作业请求器，用于请求具有有限和变化的延迟的作业以在硬件上执行加速器队列控制器，用于管理针对多个硬件加速器的处理作业请求; 以及用于将作业分派到所述多个硬件加速引擎的多个硬件队列，每个队列具有专用的队列入口头部，动态共享具有可配置队列深度限制的队列条目池，以及用于移除所有队列中的一个或多个作业的装置。

3. 发明授权

US07519793B2 Facilitating inter-DSP data communications 失效
标题翻译：促进DSP间数据通信
公开(公告)号：US07519793B2
公开(公告)日：2009-04-14
申请号：US11944028
申请日：2007-11-21
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Taylor Davis , Jeffrey Haskell Derby , Joseph Franklin Garvey , Malcolm Scott Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Taylor Davis , Jeffrey Haskell Derby , Joseph Franklin Garvey , Malcolm Scott Ware , Hua Ye
IPC分类号： G06F13/16 , G06F15/163
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
摘要翻译：一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

4. 发明申请

US20050188129A1 Facilitating inter-DSP data communications 失效
标题翻译：促进DSP间数据通信
公开(公告)号：US20050188129A1
公开(公告)日：2005-08-25
申请号：US10783757
申请日：2004-02-20
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
IPC分类号： G06F3/00 , G06F13/28 , H04L29/06
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
摘要翻译：一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

5. 发明授权

US06857065B2 System and method for system initializating a data processing system by selecting parameters from one of a user-defined input, a serial non-volatile memory and a parallel non-volatile memory 失效
标题翻译：通过从用户定义的输入，串行非易失性存储器和并行非易失性存储器之一中选择参数来系统初始化数据处理系统的系统和方法
公开(公告)号：US06857065B2
公开(公告)日：2005-02-15
申请号：US09898812
申请日：2001-07-05
申请人： Bartholomew Blaner , Arnold Steven Tran
发明人： Bartholomew Blaner , Arnold Steven Tran
IPC分类号： G06F9/445 , G06F15/177
CPC分类号： G06F9/4403
摘要： A system and method for selecting a system for initializing a data processing system. A data processing system includes, a processor coupled to a memory via an interconnect and multiple systems for initializing the aforementioned data processing system. A multiplexor is also included to select between multiple initialization systems. In the method of initializing a data processing system, an initialization or reset command is received from an external reset circuit or the processor; at least one selector signal is generated; and a set of initialization data from a selected initialization system is utilized to initialize the data processing system.
摘要翻译：一种用于选择用于初始化数据处理系统的系统的系统和方法。一种数据处理系统包括：处理器，经由互连与存储器耦合，多个系统用于初始化上述数据处理系统。还包括多路复用器以在多个初始化系统之间进行选择。在初始化数据处理系统的方法中，从外部复位电路或处理器接收初始化或复位命令; 产生至少一个选择器信号; 并且使用来自所选初始化系统的一组初始化数据来初始化数据处理系统。

6. 发明授权

US5515306A Processing system and method for minimum/maximum number determination 失效
标题翻译：最小/最大数量确定的处理系统和方法
公开(公告)号：US5515306A
公开(公告)日：1996-05-07
申请号：US388324
申请日：1995-02-14
申请人： Bartholomew Blaner , Dennis R. Strouphauer
发明人： Bartholomew Blaner , Dennis R. Strouphauer
IPC分类号： G06F7/544 , G06F9/30 , G06F7/00 , G06F7/02
CPC分类号： G06F9/30021 , G06F7/544
摘要： A data processing system with an arithmetic processing unit (ALU) and control unit is disclosed, wherein the ALU includes a first and second carry circuit and multiplexing device. Two n-bit, 2's complement operands A and B are inputted into the ALU for minimum/maximum number determination. The first carry circuit outputs a first carry into a sign bit position for the operation A+B+0, and the second carry circuit outputs a second carry into a second sign bit position for the operation A+.about.B+1. Control means for receiving minimum, minimum magnitude, maximum, and maximum magnitude operations of A and B and the carry outputs of the carry circuits outputs a control signal to the multiplexing device to output either A or B from the ALU.
摘要翻译：公开了具有算术处理单元（ALU）和控制单元的数据处理系统，其中ALU包括第一和第二进位电路和多路复用装置。两个n位，2的补码操作数A和B被输入到ALU中用于最小/最大数量确定。第一进位电路将第一进位输出到用于操作A + B + 0的符号位位置，并且第二进位电路将第二进位输出到用于操作A + DIFFERENCE B + 1的第二符号位位置。用于接收A和B的最小，最小幅度，最大和最大幅度操作的控制装置，并且进位电路的进位输出向多路复用装置输出控制信号以从ALU输出A或B.

7. 发明授权

US5504932A System for executing scalar instructions in parallel based on control bits appended by compounding decoder 失效
标题翻译：基于由复合解码器附加的控制位并行执行标量指令的系统
公开(公告)号：US5504932A
公开(公告)日：1996-04-02
申请号：US488464
申请日：1995-06-07
申请人： Stamatis Vassiliadis , Bartholomew Blaner , Thomas L. Jeremiah
发明人： Stamatis Vassiliadis , Bartholomew Blaner , Thomas L. Jeremiah
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/3017 , G06F9/3808 , G06F9/3812 , G06F9/3853 , G06F9/3885
摘要： An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch, which would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed.
摘要翻译：一种指令处理器系统，用于对由标量机的一系列基本指令产生的复合指令进行解码，该处理器产生具有指令格式文本的指令格式文本的一系列复合指令，该指令格式文本具有能够执行复合指令格式的指令格式文本中的附加控制位所述指令处理器中的文本具有复合设备，该复合设备提取和解码可由指令处理器的算术和逻辑单元作为复合指令和单个指令执行的复合指令，同时完整地保持标量机的基本指令的标量执行，最初在存储。该系统在发生可能的条件（例如分支）时，使复合指令的成员指令单元的任何执行无效，这将基于化合物的成员单元的相互关系而影响成员指令单元部分执行的记录结果的正确性指令与其他指令。所得到的一系列复合指令通常比由被执行的复合指令流的并行特性而保留的原始格式更快地执行。

8. 发明授权

US5475853A Cache store of instruction pairs with tags to indicate parallel execution 失效
标题翻译：高速缓存存储与标签的指令对以指示并行执行
公开(公告)号：US5475853A
公开(公告)日：1995-12-12
申请号：US186225
申请日：1994-01-24
申请人： Bartholomew Blaner , Stamatis Vassiliadis
发明人： Bartholomew Blaner , Stamatis Vassiliadis
IPC分类号： G06F15/00 , G06F9/00 , G06F9/38 , G06F12/08 , G06F15/76 , G06F9/06
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3853
摘要： A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
摘要翻译：一种数字计算机系统，其能够并行处理两个或更多个计算机指令，并且具有高速缓存存储单元，用于在从计算机系统的更高级存储单元到处理指令的功能单元之间临时存储机器级计算机指令。计算机系统包括位于上级存储单元的中间的指令复合单元和高速缓存存储单元，用于分析指令，并且向每个指令添加指示该指令是否可以与一个或多个并行处理的标签字段指令流中的相邻指令。然后将这些标记的指令存储在高速缓存单元中。计算机系统还包括彼此并行操作的多个功能指令处理单元。提供给这些功能单元的指令从缓存存储单元获得。在指令发布时，根据其操作代码字段的编码，检查指令的标签字段并将用于并行处理的标记字段发送到不同的功能单元。

9. 发明授权

US5423011A Apparatus for initializing branch prediction information 失效
标题翻译：用于初始化分支预测信息的装置
公开(公告)号：US5423011A
公开(公告)日：1995-06-06
申请号：US897214
申请日：1992-06-11
申请人： Bartholomew Blaner , Stamatis Vassiliadis
发明人： Bartholomew Blaner , Stamatis Vassiliadis
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/3844
摘要： Apparatus for retaining the branch prediction bits of a line displaced from an integrated cache/branch history table and using the retained bits to initialize the prediction bits should that line be brought back into the cache, the operation of which may be overlapped with the activities normally associated with displacing a cache line with one fetched from memory, thus imposing no instruction processing penalty. The apparatus consists of an associative memory that provides storage for branch prediction bits associated with cache lines and comparison means for matching stored prediction bits with their corresponding cache lines.
摘要翻译：用于保留从集成高速缓存/分支历史表中移位的行的分支预测位并使用保留的比特来初始化预测比特的装置，该线将被带回到高速缓存中，其操作可以与正常的活动重叠与从存储器中取出的一个缓存行移位相关联，因此不施加任何指令处理损失。该装置包括相关存储器，其提供与高速缓存行相关联的分支预测位的存储和用于将存储的预测位与其对应的高速缓存行进行匹配的比较装置。

10. 发明授权

US5386531A Computer system accelerator for multi-word cross-boundary storage access 失效
标题翻译：用于多字跨境存储访问的计算机系统加速器
公开(公告)号：US5386531A
公开(公告)日：1995-01-31
申请号：US700732
申请日：1991-05-15
申请人： Bartholomew Blaner , Raymond J. Eberhard , Thomas L. Jeremiah , Michael J. Mack
发明人： Bartholomew Blaner , Raymond J. Eberhard , Thomas L. Jeremiah , Michael J. Mack
IPC分类号： G06F9/312 , G06F9/38 , G06F12/04 , G06F12/06
CPC分类号： G06F9/3824 , G06F12/04 , G06F9/30043 , G06F9/3816
摘要： An instruction processing unit (IPU) and a storage array, a storage-to-instruction-processing-unit interface, including a hardware accelerator for cross-boundary storage access with a cross-boundary buffer for providing residual read and write data in support of high speed block concurrent accessing of multi-word operands of a computer system. A cross-boundary buffer (CBB) is used, coupled to a write rotating shifter, a write merger (WMERGE) and a write merge controller (WMCTL) which is coupled for an input to said control register (CREG) for sequencing data transmitted on the data bus for merger with data contained in the cross-boundary buffer (CBB) by the write merger before it is latched in a data bus out register, and for simultaneously also latching the data in the cross-boundary buffer (CBB), and for writing data from the data bus out register into the storage array in the next clock cycle of the instruction processor at the doubleword address addressed. The cross-boundary buffer (CCB) is also coupled to a read rotating shifter (RROTATE), a read merger (RMERGE) and a read merge controller which responds to control instruction sequencing. The storage-to-instruction-processing-unit interface operates on multiple words, with residues from a second and subsequent accesses allowing continuation of the accessing process beyond two memory words. The hardware can repeat a second microword until an operand of arbitrary length is transferred. The interface permits efficient data transfer to be interrupted and resumed at a desired point, for efficient execution of Load Multiple and Store Multiple operations.
摘要翻译：指令处理单元（IPU）和存储阵列，存储指令处理单元接口，包括用于跨边界存储访问的硬件加速器，用于提供冗余的读和写数据，以支持高速块并发访问计算机系统的多字操作数。使用跨边界缓冲器（CBB），耦合到写入旋转移位器，写入合并器（WMERGE）和写入合并控制器（WMCTL），写入合并控制器（WMCTL）被耦合到所述控制寄存器（CREG）的输入端，数据总线，用于与写入合并之前的数据总线输出寄存器锁存在跨界缓冲器（CBB）中的数据合并，同时还将数据锁存在跨边界缓冲器（CBB）中;以及用于将数据总线输出寄存器的数据写入指令处理器的下一个时钟周期，并以寻址的双字地址写入存储阵列。跨边界缓冲器（CCB）还耦合到读取旋转移位器（RROTATE），读取合并（RMERGE）和读取合并控制器，其响应于控制指令排序。存储到指令处理单元接口以多个字操作，具有来自第二和随后访问的残留，允许超过两个存储字的持续访问过程。硬件可以重复第二个微字直到任意长度的操作数被传送。该接口允许有效的数据传输被中断并在所需的时间点恢复，以便有效执行“加载多重”和“存储多个”操作。

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