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    • 1. 发明授权
    • Solid state memory array using address block bit substitution to
compensate for non-functional storage cells
    • 固态存储器阵列使用地址块位替换来补偿非功能存储单元
    • US5199033A
    • 1993-03-30
    • US521575
    • 1990-05-10
    • Bruce M. McGeochScott E. Richmond
    • Bruce M. McGeochScott E. Richmond
    • G11C29/00
    • G11C29/76
    • A solid state memory array includes an address bus and a bidirectional data bus and a plurality of partly defective VLSI memory array chips each containing at least one megabit of data storage capacity, having defective memory cell locations, being connected to the address bus, and providing plural data storage bit positions. Each memory array chip has a bidirectional tri-state driver connected between the bit lines thereof and corresponding ones of the data bus. At least one VLSI substitution memory chip contains at least one megabyte of data storage capacity, is connected to the address bus and provides plural data storage bit positions. A substitution chip tri-state driver is connected between the bit lines of the substitution memory chip and all of the parallel data bit lines of the data bus. A programmable read only memory is connected to be addressed by the address bus and is programmed for putting out a binary coded value which has been coded to identify each said defective memory cell location of each one of the memory array chips. A decoder is connected to receive and decode the binary coded value into tri-state driver control values and applies the values to the substitution chip tri-state driver and to one of the memory array chip bidirectional tri-state drivers so as to disable the memory array chip associated with the particular chip driver when a defective memory cell location thereof is addressed, and to enable the substitution memory chip at the particular location and connect it to the data bus in place of the associated memory array chip.
    • 固态存储器阵列包括地址总线和双向数据总线以及多个部分有缺陷的VLSI存储器阵列芯片,每个存储器阵列芯片包含连接到地址总线的具有缺陷存储器单元位置的至少一兆位的数据存储容量,并提供 多个数据存储位位置。 每个存储器阵列芯片具有连接在它们的位线和对应的数据总线之间的双向三态驱动器。 至少一个VLSI替换存储器芯片包含至少一兆字节的数据存储容量,连接到地址总线并提供多个数据存储位位置。 替代芯片三态驱动器连接在替代存储器芯片的位线和数据总线的所有并行数据位线之间。 连接可编程只读存储器以由地址总线寻址,并且被编程为输出已被编码的二进制编码值,以识别存储器阵列芯片中的每一个的每个所述缺陷存储器单元位置。 连接解码器以将二进制编码值接收并解码为三态驱动器控制值,并将该值应用于替代芯片三态驱动器和存储器阵列芯片双向三态驱动器之一,以禁用存储器 阵列芯片与特定芯片驱动器相关联,当其存储器单元的位置不正确时,并且能够使特定位置处的替换存储器芯片并且将其连接到数据总线来代替相关联的存储器阵列芯片。
    • 4. 发明授权
    • Glitchless frequency-adjustable ring oscillator
    • 无毛刺频率可调环形振荡器
    • US5471176A
    • 1995-11-28
    • US255162
    • 1994-06-07
    • James A. HensonScott E. RichmondWilliam R. Akin, Jr.
    • James A. HensonScott E. RichmondWilliam R. Akin, Jr.
    • H03K3/02G06F1/08H03K3/03H03K3/78H03L7/06H04L7/00H04L7/033H03L7/00
    • G06F1/08H03K3/0315H04L7/0083H04L7/0337
    • A clock generation circuit includes a reference clock for putting out a stable reference clocking signal. A digital ring oscillator includes a series circuit loop having at least one inverting gate and a programmable delay line of plural delays formed a series of tapped digital transmission gates connected between an output and an input of the inverting gate. A multiplexer selects among the series of taps in accordance with a tap selection signal. A clock monitoring circuit is connected to compare the clock output with a stable reference clocking signal to produce a digital clock cycle count. A programmed microcontroller generates the tap selection value as a function of the digital clock cycle count and a desired clock output frequency set point. And, a synchronization circuit synchronizes tap selection value applied to the multiplexer in relation to the present, adjustable clocking signal, and to a logical state of a successor, adjustable clocking signal to be put out by the digital ring oscillator following the tap selection, in order to avoid glitches and without interrupting oscillation.
    • 时钟生成电路包括用于输出稳定的参考时钟信号的参考时钟。 数字环形振荡器包括串联电路回路,其具有至少一个反相门和多个延迟的可编程延迟线,形成连接在反相门的输出端和输入端之间的一系列抽头数字传输门。 多路复用器根据抽头选择信号在一系列抽头之间进行选择。 连接时钟监控电路,将时钟输出与稳定的参考时钟信号进行比较,以产生数字时钟周期计数。 编程的微控制器根据数字时钟周期计数和期望的时钟输出频率设定点产生抽头选择值。 并且,同步电路将应用于多路复用器的抽头选择值与当前可调整的时钟信号相同步,并且与随后的数字环形振荡器在抽头选择之后被放出的后继可调时钟信号的逻辑状态同步, 以避免毛刺和不中断振荡。