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1. 发明申请

US20100014852A1 CSMA/CD OPTICAL INTERCONNECT SCHEME 有权
标题翻译： CSMA / CD光学互连方案
公开(公告)号：US20100014852A1
公开(公告)日：2010-01-21
申请号：US12176293
申请日：2008-07-18
申请人： Brian W. O'Krafka , Pranay Koka , John E. Cunningham , Ashok Krishnamoorthy , Xuezhe Zheng
发明人： Brian W. O'Krafka , Pranay Koka , John E. Cunningham , Ashok Krishnamoorthy , Xuezhe Zheng
IPC分类号： H04J14/00
CPC分类号： H04L12/413 , H04Q11/0062 , H04Q2011/0064 , H04Q2011/009
摘要： A method of detecting transmission collisions in an optical data interconnect system including a transmitting node, a plurality of receiving nodes, and one or more remaining nodes connected through an optical data channel. The method includes initiating a data transmission of a data signal from the transmitting node over the optical data channel, transmitting a first collision detect signal from the transmitting node throughout a duration of the data transmission where the first collision detect signal is transmitted over an optical detection channel corresponding to the transmitting node, monitoring at the transmitting node of the optical data interconnect system for a predetermined period of time, where the optical data interconnect system further includes a plurality of optical collision detection channels corresponding to each of the plurality of receiving nodes and the one or more remaining nodes, and identifying a transmission collision when a second collision signal is received through one of the plurality of optical collision detection channels at the transmitting node during the predetermined period of time.
摘要翻译：一种检测包括发送节点，多个接收节点以及通过光数据信道连接的一个或多个剩余节点的光数据互连系统中的传输冲突的方法。该方法包括通过光数据信道发起来自发射节点的数据信号的数据传输，在数据传输的持续时间内，通过光学检测发送第一冲突检测信号，从发射节点发送第一冲突检测信号信道，在光学数据互连系统的发送节点处监视预定时间段，其中光学数据互连系统还包括与多个接收节点中的每一个对应的多个光学冲突检测信道，以及所述一个或多个剩余节点，并且在所述预定时间段期间通过所述发射节点的所述多个光学冲突检测信道之一接收到第二冲突信号时，识别传输冲突。

2. 发明申请

US20100014427A1 ARBITRATION SCHEME FOR AN OPTICAL BUS 有权
标题翻译：光学总线的仲裁方案
公开(公告)号：US20100014427A1
公开(公告)日：2010-01-21
申请号：US12176294
申请日：2008-07-18
申请人： Brian W. O'Krafka , Pranay Koka , John E. Cunningham , Ashok Krishnamoorthy , Xuezhe Zheng
发明人： Brian W. O'Krafka , Pranay Koka , John E. Cunningham , Ashok Krishnamoorthy , Xuezhe Zheng
IPC分类号： G01R31/08
CPC分类号： H04L12/413
摘要： A method of arbitrating data transmissions to prevent data collisions in an optical data interconnect system including a transmitting node, a plurality of receiving nodes, and one or more remaining nodes connected through an optical data channel. The method involves transmitting a transmission request signal from the transmitting node over an arbitration channel corresponding to the transmitting node, monitoring, at the transmitting node, a plurality of arbitration channels corresponding to each of the plurality of receiving nodes and the one or more remaining nodes at the transmitting node for a predetermined period of time, determining a start time for a data transmission from the transmitting node based on the monitored signals to prevent a data collision, and initiating a data transmission of a data signal from the transmitting node over the optical data channel at the determined start time.
摘要翻译：一种仲裁数据传输的方法，以防止包括发送节点，多个接收节点以及通过光数据信道连接的一个或多个剩余节点的光数据互连系统中的数据冲突。该方法涉及通过对应于发送节点的仲裁信道从发送节点发送发送请求信号，在发送节点处监视与多个接收节点中的每一个对应的多个仲裁信道，以及一个或多个剩余节点在发送节点预定的时间段内，基于所监视的信号确定来自发送节点的数据传输的开始时间，以防止数据冲突，以及通过光学发送来自发送节点的数据信号的数据传输数据通道在确定的开始时间。

3. 发明授权

US08103165B2 Collision detection scheme for optical interconnects 有权
标题翻译：光互连的碰撞检测方案
公开(公告)号：US08103165B2
公开(公告)日：2012-01-24
申请号：US12176293
申请日：2008-07-18
申请人： Brian W. O'Krafka , Pranay Koka , John E. Cunningham , Ashok Krishnamoorthy , Xuezhe Zheng
发明人： Brian W. O'Krafka , Pranay Koka , John E. Cunningham , Ashok Krishnamoorthy , Xuezhe Zheng
IPC分类号： H04B10/08 , H04B17/00
CPC分类号： H04L12/413 , H04Q11/0062 , H04Q2011/0064 , H04Q2011/009
摘要： A method of detecting transmission collisions in an optical data interconnect system. The method includes initiating a data transmission of a data signal from a transmitting node over the optical data channel, transmitting a first collision detect signal from the transmitting node throughout a duration of the data transmission where the first collision detect signal is transmitted over an optical detection channel corresponding to the transmitting node, monitoring at the transmitting node of the optical data interconnect system for a predetermined period of time, where the optical data interconnect system further includes optical collision detection channels corresponding to each of a plurality of receiving nodes and one or more remaining nodes, and identifying a transmission collision when a second collision signal is received through one of the optical collision detection channels at the transmitting node during the predetermined period of time.
摘要翻译：一种检测光学数据互连系统中的传输冲突的方法。该方法包括通过光数据信道发起来自发射节点的数据信号的数据传输，在数据传输的持续时间内从发射节点发射第一冲突检测信号，其中第一冲突检测信号通过光学检测传输信道，在光学数据互连系统的发送节点处监视预定时间段，其中光学数据互连系统还包括与多个接收节点中的每一个对应的光学冲突检测信道和一个或多个剩余节点，并且在预定时间段期间通过发送节点的光学冲突检测信道之一接收到第二冲突信号时识别传输冲突。

4. 发明授权

US08320761B2 Broadband and wavelength-selective bidirectional 3-way optical splitter 有权
标题翻译：宽带和波长选择性双向3路光分路器
公开(公告)号：US08320761B2
公开(公告)日：2012-11-27
申请号：US11962426
申请日：2007-12-21
申请人： Xuezhe Zheng , Brian W. O'Krafka , Ashok V. Krishnamoorthy , John E. Cunningham
发明人： Xuezhe Zheng , Brian W. O'Krafka , Ashok V. Krishnamoorthy , John E. Cunningham
IPC分类号： H04J14/00 , G02B6/26 , G02B6/42
CPC分类号： G02B6/2804 , G02B6/29343 , G02B6/29352 , G02B6/43 , G02B2006/1215 , H04J14/0212 , H04Q2213/1301 , H04Q2213/13322
摘要： Embodiments of a bidirectional 3-way optical splitter are described. This bidirectional 3-way optical splitter includes an optical splitter having: a first external node, a second external node, a third external node, and a fourth external node. In one mode of operation, the optical splitter may be configured to receive an external input optical signal on the first external node and to provide external output optical signals on the other external nodes. Moreover, in another mode of operation, the optical splitter may be configured to receive the external input optical signal on the third external node and to provide the external output optical signals on the other external nodes.
摘要翻译：描述双向3路光分路器的实施例。这种双向3路光分路器包括具有：第一外部节点，第二外部节点，第三外部节点和第四外部节点的光分路器。在一种操作模式中，光分路器可以被配置为在第一外部节点上接收外部输入光信号，并且在其它外部节点上提供外部输出光信号。此外，在另一种操作模式中，光分路器可以被配置为在第三外部节点上接收外部输入光信号，并且在其它外部节点上提供外部输出光信号。

5. 发明授权

US07895400B2 Hybrid cache coherence using fine-grained hardware message passing 有权
标题翻译：混合高速缓存一致性使用细粒度的硬件消息传递
公开(公告)号：US07895400B2
公开(公告)日：2011-02-22
申请号：US11864507
申请日：2007-09-28
申请人： Brian W. O'Krafka , Pranay Koka , Robert J. Kroeger
发明人： Brian W. O'Krafka , Pranay Koka , Robert J. Kroeger
IPC分类号： G06F12/08
CPC分类号： G06F12/0837 , G06F12/0813 , G06F12/0817 , G06F2212/1016
摘要： Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware.
摘要翻译：使用全局共享存储器进行操作的多处理器系统必须确保存储器是一致的。将硬件存储器事务与直接消息传递相结合的混合系统提供了与最少占用需求或带宽需求的内存一致性。内存访问事务被拦截并转换为直接消息，然后传送到目标和/或远程节点。此后，该消息调用实现高速缓存一致性协议的软件处理程序。该处理程序使用附加消息使其他缓存中的数据无效或获取，并将数据返回到请求处理器。目标系统接口硬件将这些附加消息转换为适当的硬件事务。

6. 发明授权

US07823013B1 Hardware data race detection in HPCS codes 有权
标题翻译： HPCS代码中的硬件数据竞争检测
公开(公告)号：US07823013B1
公开(公告)日：2010-10-26
申请号：US11685555
申请日：2007-03-13
申请人： Brian W. O'Krafka , Roy S. Moore , Pranay Koka , Robert J. Kroeger
发明人： Brian W. O'Krafka , Roy S. Moore , Pranay Koka , Robert J. Kroeger
IPC分类号： G06F11/00
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/0886
摘要： A method and system for detecting race conditions computing systems. A parallel computing system includes multiple processor cores is coupled to memory. An application with a code sequence in which parallelism to be exploited is executed on this system. Different processor cores may operate on a given memory line concurrently. Extra bits are associated with the memory data line and are used to indicate changes to corresponding subsections of data in the memory line. A memory controller may perform a comparison between check bits of a memory line to determine if more than one processor core modified the same section of data in a cache line and a race condition has occurred.
摘要翻译：一种用于检测竞争条件计算系统的方法和系统。并行计算系统包括多个处理器核心耦合到存储器。具有代码序列的应用程序将在该系统上执行要利用的并行性。不同的处理器核心可以同时在给定的存储器线路上操作。额外的位与存储器数据线相关联，并且用于指示对存储器线中数据的相应子部分的改变。存储器控制器可以执行存储器线的校验位之间的比较，以确定是否有多于一个处理器核心修改了高速缓存行中的相同的数据段并且发生了竞争条件。

7. 发明申请

US20090089511A1 HYBRID CACHE COHERENCE USING FINE-GRAINED HARDWARE MESSAGE PASSING 有权
标题翻译：混合高速缓存使用细粒度硬件消息传递
公开(公告)号：US20090089511A1
公开(公告)日：2009-04-02
申请号：US11864507
申请日：2007-09-28
申请人： Brian W. O'Krafka , Pranay Koka , Robert J. Kroeger
发明人： Brian W. O'Krafka , Pranay Koka , Robert J. Kroeger
IPC分类号： G06F12/08
CPC分类号： G06F12/0837 , G06F12/0813 , G06F12/0817 , G06F2212/1016
摘要： Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware.
摘要翻译：使用全局共享存储器进行操作的多处理器系统必须确保存储器是一致的。将硬件存储器事务与直接消息传递相结合的混合系统提供了与最少占用需求或带宽需求的内存一致性。内存访问事务被拦截并转换为直接消息，然后传送到目标和/或远程节点。此后，该消息调用实现高速缓存一致性协议的软件处理程序。该处理程序使用附加消息使其他缓存中的数据无效或获取，并将数据返回到请求处理器。目标系统接口硬件将这些附加消息转换为适当的硬件事务。

8. 发明申请

US20100017572A1 TRANSACTIONAL MEMORY SUPPORT FOR NON-COHERENT SHARED MEMORY SYSTEMS USING SELECTIVE WRITE THROUGH CACHES 有权
标题翻译：使用通过快取选择性写入的非共享共享存储器系统的事务性内存支持
公开(公告)号：US20100017572A1
公开(公告)日：2010-01-21
申请号：US12176298
申请日：2008-07-18
申请人： Pranay Koka , Brian W. O'Krafka
发明人： Pranay Koka , Brian W. O'Krafka
IPC分类号： G06F12/00
CPC分类号： G06F12/0815
摘要： A method of controlling memory operations in a transactional shared memory system having a plurality of nodes connected through an interconnect network. The method includes initiating a memory operation at a first node including a first memory controller and a transaction table where the transaction table is configured to store a list of nodes affected by the memory operation, transmitting a store request signal through the interconnect network to a second node including a second memory controller and an access table where the store request signal includes memory operation data from the first memory controller, storing memory operation data to the access table in entries corresponding to one or more memory addresses affected by the memory operation, identifying a memory conflict with one or more nodes in the list of nodes when the one or more memory addresses affected by the memory operation are also affected by one or more conflicting transactions listed in the access table, transmitting an abort signal from the second node to each of the one or more nodes corresponding to the memory conflict, and transmitting an intent to commit signal from the first node to the second node.
摘要翻译：一种控制具有通过互连网络连接的多个节点的事务性共享存储器系统中的存储器操作的方法。该方法包括在包括第一存储器控制器和事务表的第一节点处启动存储器操作，其中事务表被配置为存储受存储器操作影响的节点的列表，通过互连网络将存储请求信号发送到第二节点，其包括第二存储器控制器和访问表，其中存储请求信号包括来自第一存储器控制器的存储器操作数据，将与存储器操作影响的一个或多个存储器地址相对应的条目的存储器操作数据存储到访问表中; 当由所述存储器操作影响的所述一个或多个存储器地址也受到所述访问表中列出的一个或多个冲突事务的影响时，与所述节点列表中的一个或多个节点的存储器冲突，从所述第二节点向每个节点发送中止信号与存储器相对应的一个或多个节点冲突，并发送提交签名的意图从第一个节点到第二个节点。

9. 发明申请

US20080244185A1 Reduction of cache flush time using a dirty line limiter 有权
标题翻译：使用脏线限幅器减少缓存刷新时间
公开(公告)号：US20080244185A1
公开(公告)日：2008-10-02
申请号：US11729527
申请日：2007-03-28
申请人： Brian W. O'Krafka , Roy S. Moore , Pranay Koka
发明人： Brian W. O'Krafka , Roy S. Moore , Pranay Koka
IPC分类号： G06F12/02
CPC分类号： G06F12/128 , G06F12/126
摘要： The invention relates to a method for reducing cache flush time of a cache in a computer system. The method includes populating at least one of a plurality of directory entries of a dirty line directory based on modification of the cache to form at least one populated directory entry, and de-populating a pre-determined number of the plurality of directory entries according to a dirty line limiter protocol causing a write-back from the cache to a main memory, where the dirty line limiter protocol is based on a number of the at least one populated directory entry exceeding a pre-defined limit.
摘要翻译：本发明涉及一种用于减少计算机系统中的高速缓存的高速缓冲存储器清空时间的方法。该方法包括基于高速缓存的修改来填充脏线路目录的多个目录条目中的至少一个，以形成至少一个填充的目录条目，以及根据所述多个目录条目的预定数目解除一个脏线限制器协议，其导致从缓存到主存储器的回写，其中脏线限制器协议基于至少一个填充目录条目的数量超过预定义的限制。

10. 发明授权

US08180968B2 Reduction of cache flush time using a dirty line limiter 有权
标题翻译：使用脏线限幅器减少缓存刷新时间
公开(公告)号：US08180968B2
公开(公告)日：2012-05-15
申请号：US11729527
申请日：2007-03-28
申请人： Brian W. O'Krafka , Roy S. Moore , Pranay Koka
发明人： Brian W. O'Krafka , Roy S. Moore , Pranay Koka
IPC分类号： G06F12/00
CPC分类号： G06F12/128 , G06F12/126
摘要： The invention relates to a method for reducing cache flush time of a cache in a computer system. The method includes populating at least one of a plurality of directory entries of a dirty line directory based on modification of the cache to form at least one populated directory entry, and de-populating a pre-determined number of the plurality of directory entries according to a dirty line limiter protocol causing a write-back from the cache to a main memory, where the dirty line limiter protocol is based on a number of the at least one populated directory entry exceeding a pre-defined limit.
摘要翻译：本发明涉及一种用于减少计算机系统中的高速缓存的高速缓冲存储器清空时间的方法。该方法包括基于高速缓存的修改来填充脏线路目录的多个目录条目中的至少一个，以形成至少一个填充的目录条目，以及根据所述多个目录条目的预定数目解除一个脏线限制器协议，其导致从缓存到主存储器的回写，其中脏线限制器协议基于至少一个填充目录条目的数量超过预定义的限制。

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