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1. 发明授权

US07895400B2 Hybrid cache coherence using fine-grained hardware message passing 有权
标题翻译：混合高速缓存一致性使用细粒度的硬件消息传递
公开(公告)号：US07895400B2
公开(公告)日：2011-02-22
申请号：US11864507
申请日：2007-09-28
申请人： Brian W. O'Krafka , Pranay Koka , Robert J. Kroeger
发明人： Brian W. O'Krafka , Pranay Koka , Robert J. Kroeger
IPC分类号： G06F12/08
CPC分类号： G06F12/0837 , G06F12/0813 , G06F12/0817 , G06F2212/1016
摘要： Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware.
摘要翻译：使用全局共享存储器进行操作的多处理器系统必须确保存储器是一致的。将硬件存储器事务与直接消息传递相结合的混合系统提供了与最少占用需求或带宽需求的内存一致性。内存访问事务被拦截并转换为直接消息，然后传送到目标和/或远程节点。此后，该消息调用实现高速缓存一致性协议的软件处理程序。该处理程序使用附加消息使其他缓存中的数据无效或获取，并将数据返回到请求处理器。目标系统接口硬件将这些附加消息转换为适当的硬件事务。

2. 发明授权

US07823013B1 Hardware data race detection in HPCS codes 有权
标题翻译： HPCS代码中的硬件数据竞争检测
公开(公告)号：US07823013B1
公开(公告)日：2010-10-26
申请号：US11685555
申请日：2007-03-13
申请人： Brian W. O'Krafka , Roy S. Moore , Pranay Koka , Robert J. Kroeger
发明人： Brian W. O'Krafka , Roy S. Moore , Pranay Koka , Robert J. Kroeger
IPC分类号： G06F11/00
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/0886
摘要： A method and system for detecting race conditions computing systems. A parallel computing system includes multiple processor cores is coupled to memory. An application with a code sequence in which parallelism to be exploited is executed on this system. Different processor cores may operate on a given memory line concurrently. Extra bits are associated with the memory data line and are used to indicate changes to corresponding subsections of data in the memory line. A memory controller may perform a comparison between check bits of a memory line to determine if more than one processor core modified the same section of data in a cache line and a race condition has occurred.
摘要翻译：一种用于检测竞争条件计算系统的方法和系统。并行计算系统包括多个处理器核心耦合到存储器。具有代码序列的应用程序将在该系统上执行要利用的并行性。不同的处理器核心可以同时在给定的存储器线路上操作。额外的位与存储器数据线相关联，并且用于指示对存储器线中数据的相应子部分的改变。存储器控制器可以执行存储器线的校验位之间的比较，以确定是否有多于一个处理器核心修改了高速缓存行中的相同的数据段并且发生了竞争条件。

3. 发明申请

US20090089511A1 HYBRID CACHE COHERENCE USING FINE-GRAINED HARDWARE MESSAGE PASSING 有权
标题翻译：混合高速缓存使用细粒度硬件消息传递
公开(公告)号：US20090089511A1
公开(公告)日：2009-04-02
申请号：US11864507
申请日：2007-09-28
申请人： Brian W. O'Krafka , Pranay Koka , Robert J. Kroeger
发明人： Brian W. O'Krafka , Pranay Koka , Robert J. Kroeger
IPC分类号： G06F12/08
CPC分类号： G06F12/0837 , G06F12/0813 , G06F12/0817 , G06F2212/1016
摘要： Multiprocessor systems conducting operations utilizing global shared memory must ensure that the memory is coherent. A hybrid system that combines hardware memory transactions with that of direct messaging provides memory coherence with minimal overhead requirement or bandwidth demands. Memory access transactions are intercepted and converted to direct messages which are then communicated to a target and/or remote node. Thereafter the message invokes a software handler which implements the cache coherence protocol. The handler uses additional messages to invalidate or fetch data in other caches, as well as to return data to the requesting processor. These additional messages are converted to appropriate hardware transactions by the destination system interface hardware.
摘要翻译：使用全局共享存储器进行操作的多处理器系统必须确保存储器是一致的。将硬件存储器事务与直接消息传递相结合的混合系统提供了与最少占用需求或带宽需求的内存一致性。内存访问事务被拦截并转换为直接消息，然后传送到目标和/或远程节点。此后，该消息调用实现高速缓存一致性协议的软件处理程序。该处理程序使用附加消息使其他缓存中的数据无效或获取，并将数据返回到请求处理器。目标系统接口硬件将这些附加消息转换为适当的硬件事务。

4. 发明授权

US07929526B2 Direct messaging in distributed memory systems 失效
标题翻译：分布式存储系统中的直接消息传递
公开(公告)号：US07929526B2
公开(公告)日：2011-04-19
申请号：US11864414
申请日：2007-09-28
申请人： Robert J. Kroeger , Brian W. O'Krafka , Pranay Koka
发明人： Robert J. Kroeger , Brian W. O'Krafka , Pranay Koka
IPC分类号： H04L12/28 , H04L12/56 , G06F15/16 , G06F9/26
CPC分类号： G06F15/173 , H04L69/12
摘要： A system and method for sending a cache line of data in a single message is described. An instruction issued by a processor in a multiprocessor system includes an address of a message payload and an address of a destination. Each address is translated to a physical address and sent to a scalability interface associated with the processor and in communication with a system interconnect. Upon translation the payload of the instruction is written to the scalability interface and thereafter communicated to the destination. According to one embodiment, the translation of the payload address is accomplished by the processor while in another embodiment the translation occurs at the scalability interface.
摘要翻译：描述用于在单个消息中发送数据的高速缓存行的系统和方法。处理器在多处理器系统中发出的指令包括消息有效载荷的地址和目的地的地址。每个地址被转换为物理地址并发送到与处理器相关联并与系统互连通信的可扩展性接口。翻译后，指令的有效载荷被写入可扩展性接口，然后传送到目的地。根据一个实施例，有效载荷地址的翻译由处理器完成，而在另一实施例中，翻译发生在可伸缩性界面处。

5. 发明申请

US20090086746A1 DIRECT MESSAGING IN DISTRIBUTED MEMORY SYSTEMS 失效
标题翻译：分布式存储系统中的直接消息传递
公开(公告)号：US20090086746A1
公开(公告)日：2009-04-02
申请号：US11864414
申请日：2007-09-28
申请人： Robert J. Kroeger , Brian W. O'Krafka , Pranay Koka
发明人： Robert J. Kroeger , Brian W. O'Krafka , Pranay Koka
IPC分类号： H04L12/56
CPC分类号： G06F15/173 , H04L69/12
摘要： A system and method for sending a cache line of data in a single message is described. An instruction issued by a processor in a multiprocessor system includes an address of a message payload and an address of a destination. Each address is translated to a physical address and sent to a scalability interface associated with the processor and in communication with a system interconnect. Upon translation the payload of the instruction is written to the scalability interface and thereafter communicated to the destination. According to one embodiment, the translation of the payload address is accomplished by the processor while in another embodiment the translation occurs at the scalability interface.
摘要翻译：描述用于在单个消息中发送数据的高速缓存行的系统和方法。处理器在多处理器系统中发出的指令包括消息有效载荷的地址和目的地的地址。每个地址被转换为物理地址并发送到与处理器相关联并与系统互连通信的可扩展性接口。翻译后，指令的有效载荷被写入可扩展性接口，然后传送到目的地。根据一个实施例，有效载荷地址的翻译由处理器完成，而在另一实施例中，翻译发生在可伸缩性界面处。

6. 发明授权

US09086914B2 System and method for reducing startup cost of a software application 有权
标题翻译：降低软件应用启动成本的系统和方法
公开(公告)号：US09086914B2
公开(公告)日：2015-07-21
申请号：US13569002
申请日：2012-08-07
申请人： Matthew J. Bolohan , Robert J. Kroeger , Aleksandr V. Kennberg
发明人： Matthew J. Bolohan , Robert J. Kroeger , Aleksandr V. Kennberg
IPC分类号： G06F15/16 , G06F9/48
CPC分类号： G06F9/4843
摘要： A computing device has one or more processors and memory storing programs executed by the one or more processors. The computing device initializes a main application on a first thread. The main application has a first synchronous connection with a target application. After the main application performs one or more operations at the target application through the first synchronous connection, the computing device initializes an assistant process on a second thread. The assistant process has a second synchronous connection with the target application and an asynchronous connection with the main application. After receiving a request from the main application through the asynchronous connection, the assistant process performs one or more operations at the target application through the second synchronous connection.
摘要翻译：计算设备具有由一个或多个处理器执行的一个或多个处理器和存储器存储程序。计算设备在第一个线程上初始化主应用程序。主应用程序与目标应用程序具有第一个同步连接。在主应用程序通过第一同步连接在目标应用程序执行一个或多个操作之后，计算设备在第二线程上初始化辅助处理。辅助进程与目标应用程序进行第二次同步连接，并与主应用程序进行异步连接。通过异步连接从主应用程序接收到请求后，辅助进程通过第二同步连接在目标应用程序执行一个或多个操作。

7. 发明申请

US20120047422A1 HOVERCARD PIVOTING FOR MOBILE DEVICES 有权
标题翻译：移动设备租赁
公开(公告)号：US20120047422A1
公开(公告)日：2012-02-23
申请号：US12983982
申请日：2011-01-04
申请人： Alexander Nicolaou , Joanne L. McKinley , Robert J. Kroeger , Brett R. Lider , Istiaque Ahmed
发明人： Alexander Nicolaou , Joanne L. McKinley , Robert J. Kroeger , Brett R. Lider , Istiaque Ahmed
IPC分类号： G06F17/00 , G06F3/048
CPC分类号： G06F17/30873 , G06F3/0481 , G06F3/04842 , G06F17/2235 , G06F17/30893
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for invoking execution of web based applications. In one aspect, a method includes receiving user input at a computing device, displaying a contact hovercard on a display of the computing device in response to the user input, the contact hovercard including first contact data and second contact data, the first contact data corresponding to a first web application and the second contact data corresponding to a second web application, the first web application and the second web application being executed on one or more servers, receiving user input selecting the first contact data, generating a user interface and accessing the first web application over a network in response to receiving the user input selecting the first contact data, and providing the first contact data as input to the first web application.
摘要翻译：方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于调用基于web的应用的执行。一方面，一种方法包括在计算设备处接收用户输入，响应于用户输入在计算设备的显示器上显示联系人悬停卡，所述联系人悬停卡包括第一联系人数据和第二联系人数据，所述第一联系人数据对应到第一web应用程序和对应于第二Web应用程序的第二联系人数据，第一web应用程序和第二web应用程序在一个或多个服务器上执行，接收选择第一联系人数据的用户输入，生成用户界面并访问响应于接收到所述用户输入选择所述第一联系人数据，并且将所述第一联系人数据提供给所述第一web应用程序的输入，通过网络进行第一web应用程序。

8. 发明授权

US09165081B2 Hovercard pivoting for mobile devices 有权
标题翻译：移动设备旋转卡盘
公开(公告)号：US09165081B2
公开(公告)日：2015-10-20
申请号：US12983982
申请日：2011-01-04
申请人： Alexander Nicolaou , Joanne L. McKinley , Robert J. Kroeger , Brett R. Lider , Istiaque Ahmed
发明人： Alexander Nicolaou , Joanne L. McKinley , Robert J. Kroeger , Brett R. Lider , Istiaque Ahmed
IPC分类号： G06F17/30 , G06F3/0484 , G06F3/0481 , G06F17/22
CPC分类号： G06F17/30873 , G06F3/0481 , G06F3/04842 , G06F17/2235 , G06F17/30893
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for invoking execution of web based applications. In one aspect, a method includes receiving user input at a computing device, displaying a contact hovercard on a display of the computing device in response to the user input, the contact hovercard including first contact data and second contact data, the first contact data corresponding to a first web application and the second contact data corresponding to a second web application, the first web application and the second web application being executed on one or more servers, receiving user input selecting the first contact data, generating a user interface and accessing the first web application over a network in response to receiving the user input selecting the first contact data, and providing the first contact data as input to the first web application.
摘要翻译：方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于调用基于web的应用的执行。一方面，一种方法包括在计算设备处接收用户输入，响应于用户输入在计算设备的显示器上显示联系人悬停卡，所述联系人悬停卡包括第一联系人数据和第二联系人数据，所述第一联系人数据对应到第一web应用程序和对应于第二Web应用程序的第二联系人数据，第一web应用程序和第二web应用程序在一个或多个服务器上执行，接收选择第一联系人数据的用户输入，生成用户界面并访问响应于接收到所述用户输入选择所述第一联系人数据，并且将所述第一联系人数据提供给所述第一web应用程序的输入，通过网络进行第一web应用程序。

9. 发明申请

US20120303756A1 SYSTEM AND METHOD FOR REDUCING STARTUP COST OF A SOFTWARE APPLICATION 有权
标题翻译：降低软件应用启动成本的系统和方法
公开(公告)号：US20120303756A1
公开(公告)日：2012-11-29
申请号：US13569002
申请日：2012-08-07
申请人： Matthew J. Bolohan , Robert J. Kroeger , Aleksandr V. Kennberg
发明人： Matthew J. Bolohan , Robert J. Kroeger , Aleksandr V. Kennberg
IPC分类号： G06F15/16
CPC分类号： G06F9/4843
摘要： A computing device has one or more processors and memory storing programs executed by the one or more processors. The computing device initializes a main application on a first thread. The main application has a first synchronous connection with a target application. After the main application performs one or more operations at the target application through the first synchronous connection, the computing device initializes an assistant process on a second thread. The assistant process has a second synchronous connection with the target application and an asynchronous connection with the main application. After receiving a request from the main application through the asynchronous connection, the assistant process performs one or more operations at the target application through the second synchronous connection.
摘要翻译：计算设备具有由一个或多个处理器执行的一个或多个处理器和存储器存储程序。计算设备在第一个线程上初始化主应用程序。主应用程序与目标应用程序具有第一个同步连接。在主应用程序通过第一同步连接在目标应用程序执行一个或多个操作之后，计算设备在第二线程上初始化辅助处理。辅助进程与目标应用程序进行第二次同步连接，并与主应用程序进行异步连接。通过异步连接从主应用程序接收到请求后，辅助进程通过第二同步连接在目标应用程序执行一个或多个操作。

10. 发明授权

US07631171B2 Method and apparatus for supporting vector operations on a multi-threaded microprocessor 有权
标题翻译：用于在多线程微处理器上支持向量操作的方法和装置
公开(公告)号：US07631171B2
公开(公告)日：2009-12-08
申请号：US11312853
申请日：2005-12-19
申请人： Jan L. Bonebakker , Robert J. Kroeger
发明人： Jan L. Bonebakker , Robert J. Kroeger
IPC分类号： G06F9/44 , G06F9/30 , G06F9/455
CPC分类号： G06F9/3851 , G06F9/3001 , G06F9/30036 , G06F9/3885
摘要： One embodiment of the present invention provides a system that supports vector operations on a multi-threaded microprocessor. During operation, the system detects a vector instruction in a program. The system maps this vector instruction onto the thread contexts of the multi-threaded microprocessor. As part of the mapping process, the system splits the vector instruction across a set of threads that execute in parallel and generates a set of instructions for the set of threads. This mapping process allows the vector instruction to be executed efficiently across multiple threads.
摘要翻译：本发明的一个实施例提供了一种在多线程微处理器上支持向量操作的系统。在运行期间，系统检测程序中的向量指令。该系统将该向量指令映射到多线程微处理器的线程上下文。作为映射过程的一部分，系统将跨越并行执行的一组线程分割向量指令，并为该组线程生成一组指令。该映射过程允许在多个线程上有效地执行向量指令。

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