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1. 发明授权

US06566190B2 Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices 失效
标题翻译：垂直内部连接的沟槽单元（V-ICTC）和半导体存储器件的形成方法
公开(公告)号：US06566190B2
公开(公告)日：2003-05-20
申请号：US09941689
申请日：2001-08-30
申请人： Brian S. Lee , John Walsh
发明人： Brian S. Lee , John Walsh
IPC分类号： H01L2994
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L27/10876 , H01L27/1203 , H01L29/66181
摘要： A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that required for a conventional buried strap trench (BEST) cell without causing any negative impact on device performance. The lower cell capacitance also extends the feasibility of deep trench capacitor manufacturing technology without requiring new materials or processing methods. A method of manufacturing the DRAM includes forming a very thin Si layer on top of a DT cell while at the same time the method forms an isolated layer replacing a conventional collar. The formation of the SOI by internal thermal oxidation (ITO) makes the structure in such a manner that the device may be fully depleted.
摘要翻译：具有垂直晶体管和内部连接的带（ICS）的动态随机存取存储器（DRAM）器件，用于将晶体管连接到电容器。 ICS不与基板直接接触。 DRAM单元以比常规掩埋带沟槽（BEST）单元所需的电容小得多的单元电容器工作，而不会对器件性能造成任何负面影响。较低的电池电容也扩大了深沟槽电容器制造技术的可行性，而不需要新的材料或加工方法。制造DRAM的方法包括在DT单元的顶部上形成非常薄的Si层，同时该方法形成代替传统套环的隔离层。通过内部热氧化（ITO）形成SOI使得该装置可以完全耗尽。

2. 发明授权

US06828615B2 Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices 有权
标题翻译：垂直内部连接的沟槽单元（V-ICTC）和半导体存储器件的形成方法
公开(公告)号：US06828615B2
公开(公告)日：2004-12-07
申请号：US10314131
申请日：2002-12-09
申请人： Brian S. Lee , John Walsh
发明人： Brian S. Lee , John Walsh
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , H01L27/1203
摘要： A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that required for a conventional buried strap trench (BEST) cell without causing any negative impact on device performance. The lower cell capacitance also extends the feasibility of deep trench capacitor manufacturing technology without requiring new materials or processing methods. A method of manufacturing the DRAM includes forming a very thin Si layer on top of a DT cell while at the same time the method forms an isolated layer replacing a conventional collar. The formation of the SOI by internal thermal oxidation (ITO) makes the structure in such a manner that the device may be fully depleted.
摘要翻译：具有垂直晶体管和内部连接的带（ICS）的动态随机存取存储器（DRAM）器件，用于将晶体管连接到电容器。 ICS不与基板直接接触。 DRAM单元以比常规掩埋带沟槽（BEST）单元所需的电容小得多的单元电容器工作，而不会对器件性能造成任何负面影响。较低的电池电容也扩大了深沟槽电容器制造技术的可行性，而不需要新的材料或加工方法。制造DRAM的方法包括在DT单元的顶部上形成非常薄的Si层，同时该方法形成代替传统套环的隔离层。通过内部热氧化（ITO）形成SOI使得该装置可以完全耗尽。

3. 发明授权

US06770954B2 Semiconductor device with SI-GE layer-containing low resistance, tunable contact 有权
标题翻译：具有SI-GE层的低电阻半导体器件，可调触点
公开(公告)号：US06770954B2
公开(公告)日：2004-08-03
申请号：US10305147
申请日：2002-11-27
申请人： Brian S. Lee , John Walsh
发明人： Brian S. Lee , John Walsh
IPC分类号： H01L31117
CPC分类号： H01L21/28518 , H01L21/28525 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76859 , H01L21/823871
摘要： The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1−x (0
摘要翻译：本发明提供一种半导体器件，其中通过使用SixGe1-x（0

4. 发明授权

US06511905B1 Semiconductor device with Si-Ge layer-containing low resistance, tunable contact 有权
标题翻译：具有Si-Ge层的低电阻半导体器件，可调触点
公开(公告)号：US06511905B1
公开(公告)日：2003-01-28
申请号：US10035221
申请日：2002-01-04
申请人： Brian S. Lee , John Walsh
发明人： Brian S. Lee , John Walsh
IPC分类号： H01L214763
CPC分类号： H01L21/28518 , H01L21/28525 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76859 , H01L21/823871
摘要： The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1−x (0
摘要翻译：本发明提供一种半导体器件，其中通过使用SixGe1-x（0

5. 发明授权

US06939763B2 DRAM cell arrangement with vertical MOS transistors, and method for its fabrication 失效
标题翻译：具有垂直MOS晶体管的DRAM单元布置及其制造方法
公开(公告)号：US06939763B2
公开(公告)日：2005-09-06
申请号：US10720730
申请日：2003-11-24
申请人： Till Schlösser , Brian S. Lee
发明人： Till Schlösser , Brian S. Lee
IPC分类号： H01L21/02 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/786
CPC分类号： H01L27/10858 , H01L27/10852 , H01L27/10876
摘要： DRAM cell arrangement with vertical MOS transistors, and method for its fabrication. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.
摘要翻译：具有垂直MOS晶体管的DRAM单元布置及其制造方法。沿着存储单元矩阵的一列排列的通道区域是由栅介质层包围的肋的部分。属于一行的MOS晶体管的栅电极是条状字线的一部分，因此在存储单元矩阵的每个交叉点存在垂直双栅极MOS晶体管，其中形成相关联的字线的栅电极相关肋骨两侧的沟槽。

6. 发明申请

US20100103717A1 TUNING A VARIABLE RESISTANCE OF A RESISTIVE SENSE ELEMENT 有权
标题翻译：调整电阻感知元件的可变电阻
公开(公告)号：US20100103717A1
公开(公告)日：2010-04-29
申请号：US12497929
申请日：2009-07-06
申请人： Brian S. Lee , Haiwen Xi , Patrick J. Ryan , Rod Bowman
发明人： Brian S. Lee , Haiwen Xi , Patrick J. Ryan , Rod Bowman
IPC分类号： G11C11/00
CPC分类号： G11C29/02 , G11C7/06 , G11C11/22 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C29/026 , G11C29/028 , G11C29/50008 , G11C2013/0073 , G11C2207/2254 , G11C2213/31
摘要： Method and apparatus for tuning a variable resistance resistive sense element of an electronic device. In some embodiments, a value indicative of a selected number of consecutive pulses is stored in a memory location and a resistive sense element (RSE) is set to a baseline RSE resistance. A tuning operation is performed by applying the selected number of consecutive pulses to the RSE to tune the baseline RSE resistance to a final adjusted resistance.
摘要翻译：用于调谐电子设备的可变电阻电阻感测元件的方法和装置。在一些实施例中，将指示所选数量的连续脉冲的值存储在存储器位置中，并且将电阻感测元件（RSE）设置为基线RSE电阻。通过将所选数量的连续脉冲施加到RSE来执行调谐操作，以将基线RSE电阻调谐到最终调整的电阻。

7. 发明授权

US06372567B1 Control of oxide thickness in vertical transistor structures 有权
标题翻译：垂直晶体管结构中氧化物厚度的控制
公开(公告)号：US06372567B1
公开(公告)日：2002-04-16
申请号：US09553708
申请日：2000-04-20
申请人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening
发明人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening
IPC分类号： H01L218238
CPC分类号： H01L21/28211 , H01L21/2236 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/28238 , H01L27/10864 , H01L27/10873 , H01L29/045
摘要： Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment for a period sufficient to generate an amorphous layer of oxide side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.
摘要翻译：在DRAM中制备垂直晶体管结构的改进方法，其中沟槽顶部氧化物将底部存储电容器与开关晶体管分离，并且其中沟槽的上部在其侧壁处包含垂直晶体管，以获得均匀的栅极氧化沟槽内的所有不同的晶面，使得均匀的厚度与晶体取向无关，包括：a）使晶片沟槽侧壁进行离子轰击足以产生氧化物侧壁的非晶层的时间; 和b）在氧化气氛中加热由步骤（a）得到的晶片，以引起非晶层的氧化和重结晶。

8. 发明授权

US07087947B2 Semiconductor device with loop line pattern structure, method and alternating phase shift mask for fabricating the same 有权
标题翻译：具有环线图案结构的半导体器件，用于制造其的交替相移掩模
公开(公告)号：US07087947B2
公开(公告)日：2006-08-08
申请号：US10957688
申请日：2004-10-05
申请人： Brian S. Lee , Chih-Yu Lee
发明人： Brian S. Lee , Chih-Yu Lee
IPC分类号： H01L27/108
CPC分类号： H01L21/32139 , G03F1/30 , H01L27/10861 , H01L27/10891
摘要： An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.
摘要翻译：具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区域或栅极线。通过使用交替相移掩模来对DRAM阵列中的栅极线或有源区进行图案化，在DRAM阵列中不产生不需要的图像，并且仅需要一次曝光来实现高分辨率要求。

9. 发明授权

US06544888B2 Advanced contact integration scheme for deep-sub-150 nm devices 有权
标题翻译：深层次的150纳米器件的高级接触集成方案
公开(公告)号：US06544888B2
公开(公告)日：2003-04-08
申请号：US09892620
申请日：2001-06-28
申请人： Brian S. Lee
发明人： Brian S. Lee
IPC分类号： H01L2144
CPC分类号： H01L21/76895 , H01L21/28518 , H01L21/823871
摘要： An advanced contact integration technique for deep-sub-150 nm semiconductor devices such as W/WN gate electrodes, dual work function gates, dual gate MOSFETs and SOI devices. This technique integrates self-aligned raised source/drain contact processes with a process employing a W-Salicide combined with ion mixing implantation. The contact integration technique realizes junctions having low contact resistance (RC), with ultra-shallow contact junction depth (XJC) and high doping concentration in the silicide contact interface (Nc).
摘要翻译：用于深 - 150nm半导体器件（例如W / WN栅电极，双功函数栅极，双栅MOSFET和SOI器件）的先进接触积分技术。该技术将自对准凸起源极/漏极接触过程与采用W-Salicide结合离子混合植入的方法相结合。接触积分技术实现了具有低接触电阻（RC）的接点，具有超浅接触结深度（XJC）和硅化物接触界面（Nc）中的高掺杂浓度。

10. 发明授权

US06426253B1 Method of forming a vertically oriented device in an integrated circuit 有权
标题翻译：在集成电路中形成垂直取向器件的方法
公开(公告)号：US06426253B1
公开(公告)日：2002-07-30
申请号：US09576465
申请日：2000-05-23
申请人： Helmut Horst Tews , Alexander Michaelis , Brian S. Lee , Uwe Schroeder , Stephan Kudelka
发明人： Helmut Horst Tews , Alexander Michaelis , Brian S. Lee , Uwe Schroeder , Stephan Kudelka
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/76237 , H01L21/823487 , H01L27/10841 , H01L27/10867
摘要： A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.
摘要翻译：使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或在沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分沟槽暴露进一步加工。或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

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