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    • 1. 发明授权
    • Network adapter with host indication optimization
    • 具有主机指示优化的网络适配器
    • US5307459A
    • 1994-04-26
    • US920898
    • 1992-07-28
    • Brian PetersenW. Paul ShererDavid R. BrownLai-Chin Lo
    • Brian PetersenW. Paul ShererDavid R. BrownLai-Chin Lo
    • G06F13/00G06F13/12H04L29/06H04L29/10
    • G06F13/128H04L29/06
    • Optimized indication signals of a completed data frame transfer are generated by a network adapter which reduces host processor interrupt latency. The network adapter comprises network interface logic for transferring the data frame between the network and a buffer memory and host interface logic for transferring the data frame between the buffer memory and the host system. The network adapter further includes threshold logic where a threshold value in an alterable storage location is compared to a data transfer counter in order to generate an early indication signal. The early indication signal may be used to generate an early interrupt signal to a host processor before a transfer of a data frame is completed. The network adapter also posts status information status registers which may be used by the host processor to tune the timing of the generation of the network adapter interrupt signal.
    • 完成的数据帧传输的优化指示信号由减少主处理器中断延迟的网络适配器产生。 网络适​​配器包括用于在网络和缓冲存储器之间传送数据帧的网络接口逻辑和用于在缓冲存储器和主机系统之间传送数据帧的主机接口逻辑。 网络适​​配器还包括阈值逻辑,其中可变存储位置中的阈值与数据传送计数器进行比较,以便生成早期指示信号。 早期指示信号可以用于在数据帧的传送完成之前向主处理器产生早期中断信号。 网络适​​配器还布置状态信息状态寄存器,其可由主机处理器使用以调整生成网络适配器中断信号的时序。
    • 2. 发明授权
    • Network interface with host independent buffer management
    • 具有主机独立缓存管理的网络接口
    • US5299313A
    • 1994-03-29
    • US921519
    • 1992-07-28
    • Brian PetersenW. Paul ShererDavid R. BrownLai-Chin Lo
    • Brian PetersenW. Paul ShererDavid R. BrownLai-Chin Lo
    • G06F13/00G06F13/12H04L13/08
    • G06F13/128
    • A network interface controller controls communication between a host system and a network transceiver coupled to a network comprises a memory outside of the host address space in which receive and transmit buffers are managed, host interface logic emulating memory mapped registers in the host address space, for transferring data between the host address space and the buffer memory, and network interface logic coupled with the network transceiver, for transferring data between the buffers in the buffer memory and the network transceiver. The buffer memory includes a transmit descriptor ring buffer, transmit data buffer, transfer descriptor buffer, and receive ring buffer all managed by operations transparent to the host.
    • 网络接口控制器控制主机系统和耦合到网络的网络收发器之间的通信,包括主机地址空间外的存储器,其中管理接收和发送缓冲器的主机接口逻辑,模拟主机地址空间中的存储器映射寄存器,用于 在主机地址空间和缓冲存储器之间传送数据,以及与网络收发器耦合的网络接口逻辑,用于在缓冲存储器中的缓冲器和网络收发器之间传送数据。 缓冲存储器包括发送描述符环形缓冲器,发送数据缓冲器,传输描述符缓冲器和接收环形缓冲器,全部由对主机透明的操作管理。
    • 5. 发明授权
    • Network adapter with an indication signal mask and an interrupt signal
mask
    • 具有指示信号掩码和中断信号掩码的网络适配器
    • US5530874A
    • 1996-06-25
    • US012561
    • 1993-02-02
    • Scott A. EmeryBrian PetersenW. Paul Sherer
    • Scott A. EmeryBrian PetersenW. Paul Sherer
    • G06F13/00G06F13/24G06F9/46
    • G06F13/24
    • Indication and interrupt signals generated by a network adapter representing asynchronous events are managed by a host system. The network adapter includes a first mask logic for selectively disabling the indication signals from being stored in a first memory location by the host writing to a first mask register. A second mask logic which is coupled to the first memory location also selectively disables the indication signals from being stored in a second memory location creating two levels of status information. The indication signals may also be disabled from being stored in the second memory location responsive to the host writing to a second mask register. The first memory location may be read from the host in order to determine whether a network event occurred during an interrupt service routine, while interrupt means generates an interrupt signal to the host responsive to the value in the second memory location. A third level of control is provided by an internal counter which allows for automatic enabling and/or disabling of a plurality of indications and interrupts with and without explicit commands in the host driver subroutines.
    • 由代表异步事件的网络适配器产生的指示和中断信号由主机系统管理。 网络适​​配器包括第一屏蔽逻辑,用于通过主机向第一屏蔽寄存器写入来选择性地禁用指示信号存储在第一存储器位置。 耦合到第一存储器位置的第二掩模逻辑还选择性地禁止指示信号被存储在创建两级状态信息的第二存储器位置中。 响应于主机向第二屏蔽寄存器的写入,也可以禁止指示信号存储在第二存储单元中。 可以从主机读取第一存储器位置,以便确定在中断服务程序期间是否发生网络事件,而中断装置响应于第二存储器位置中的值产生对主机的中断信号。 第三级控制由内部计数器提供,其允许在主机驱动程序子程序中使用和不使用显式命令来自动启用和/或禁用多个指示和中断。
    • 10. 发明授权
    • Method for optimizing software for any one of a plurality of variant
architectures
    • 用于优化多个变体架构中的任何一个的软件的方法
    • US5459854A
    • 1995-10-17
    • US727824
    • 1991-07-09
    • W. Paul ShererGlenn W. ConneryScott A. Emery
    • W. Paul ShererGlenn W. ConneryScott A. Emery
    • G06F9/445G06F12/02G06F9/24G06F15/177
    • G06F12/023G06F9/44547
    • A method allows a designer to implement software for a wide variety of variant host architectures, without excessive usage of host memory, nor sacrificing the capabilities of high end versions of the variant architectures available. The method is based on providing an initialization module of the software to host memory. A portion of the initialization module determines the host architecture. Based on the determined host architecture, the unneeded portions of the initialization module are freed, and the needed portions are relocated into a contiguous memory space to minimize host memory usage. Any location dependent entries in the needed portions of the program are then updated based on the relocation. The initialization module includes a plurality of code blocks, each of which is optimized to a particular variant architecture. When the variant architecture of the host is identified, those code blocks which are optimized to the identified host are selected and the other code blocks are freed. The selected blocks are then relocated to optimize host memory usage.
    • 一种方法允许设计人员为多种不同的主机架构实现软件,而不会过多地使用主机内存,也不会牺牲可用的变体架构的高端版本的功能。 该方法基于提供软件的初始化模块来主机存储器。 初始化模块的一部分确定主机架构。 基于确定的主机架构,初始化模块的不需要的部分被释放,并且所需部分被重新定位到连续的存储器空间中以最小化主机存储器使用。 然后根据重定位更新程序所需部分中的任何位置相关条目。 初始化模块包括多个代码块,每个代码块针对特定的变体架构被优化。 当识别主机的变体架构时,选择对识别的主机优化的代码块,并且释放其他代码块。 然后重新定位所选择的块以优化主机内存使用。