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1. 发明授权

US5299313A Network interface with host independent buffer management 失效
标题翻译：具有主机独立缓存管理的网络接口
公开(公告)号：US5299313A
公开(公告)日：1994-03-29
申请号：US921519
申请日：1992-07-28
申请人： Brian Petersen , W. Paul Sherer , David R. Brown , Lai-Chin Lo
发明人： Brian Petersen , W. Paul Sherer , David R. Brown , Lai-Chin Lo
IPC分类号： G06F13/00 , G06F13/12 , H04L13/08
CPC分类号： G06F13/128
摘要： A network interface controller controls communication between a host system and a network transceiver coupled to a network comprises a memory outside of the host address space in which receive and transmit buffers are managed, host interface logic emulating memory mapped registers in the host address space, for transferring data between the host address space and the buffer memory, and network interface logic coupled with the network transceiver, for transferring data between the buffers in the buffer memory and the network transceiver. The buffer memory includes a transmit descriptor ring buffer, transmit data buffer, transfer descriptor buffer, and receive ring buffer all managed by operations transparent to the host.
摘要翻译：网络接口控制器控制主机系统和耦合到网络的网络收发器之间的通信，包括主机地址空间外的存储器，其中管理接收和发送缓冲器的主机接口逻辑，模拟主机地址空间中的存储器映射寄存器，用于在主机地址空间和缓冲存储器之间传送数据，以及与网络收发器耦合的网络接口逻辑，用于在缓冲存储器中的缓冲器和网络收发器之间传送数据。缓冲存储器包括发送描述符环形缓冲器，发送数据缓冲器，传输描述符缓冲器和接收环形缓冲器，全部由对主机透明的操作管理。

2. 发明授权

US5307459A Network adapter with host indication optimization 失效
标题翻译：具有主机指示优化的网络适配器
公开(公告)号：US5307459A
公开(公告)日：1994-04-26
申请号：US920898
申请日：1992-07-28
申请人： Brian Petersen , W. Paul Sherer , David R. Brown , Lai-Chin Lo
发明人： Brian Petersen , W. Paul Sherer , David R. Brown , Lai-Chin Lo
IPC分类号： G06F13/00 , G06F13/12 , H04L29/06 , H04L29/10
CPC分类号： G06F13/128 , H04L29/06
摘要： Optimized indication signals of a completed data frame transfer are generated by a network adapter which reduces host processor interrupt latency. The network adapter comprises network interface logic for transferring the data frame between the network and a buffer memory and host interface logic for transferring the data frame between the buffer memory and the host system. The network adapter further includes threshold logic where a threshold value in an alterable storage location is compared to a data transfer counter in order to generate an early indication signal. The early indication signal may be used to generate an early interrupt signal to a host processor before a transfer of a data frame is completed. The network adapter also posts status information status registers which may be used by the host processor to tune the timing of the generation of the network adapter interrupt signal.
摘要翻译：完成的数据帧传输的优化指示信号由减少主处理器中断延迟的网络适配器产生。网络适配器包括用于在网络和缓冲存储器之间传送数据帧的网络接口逻辑和用于在缓冲存储器和主机系统之间传送数据帧的主机接口逻辑。网络适配器还包括阈值逻辑，其中可变存储位置中的阈值与数据传送计数器进行比较，以便生成早期指示信号。早期指示信号可以用于在数据帧的传送完成之前向主处理器产生早期中断信号。网络适配器还布置状态信息状态寄存器，其可由主机处理器使用以调整生成网络适配器中断信号的时序。

3. 发明授权

US5392406A DMA data path aligner and network adaptor utilizing same 失效
标题翻译： DMA数据路径对齐器和使用相同的网络适配器
公开(公告)号：US5392406A
公开(公告)日：1995-02-21
申请号：US947055
申请日：1992-09-18
申请人： Brian Petersen , Lai-Chin Lo , David R. Brown
发明人： Brian Petersen , Lai-Chin Lo , David R. Brown
IPC分类号： G06F5/00 , G06F13/28 , G06F13/40 , G06F13/00
CPC分类号： G06F5/00 , G06F13/28 , G06F13/4013
摘要： A data path aligner transfers data from an input having N byte lanes with byte enable bits to an output having N byte lanes. The aligner includes first stage having N-1 selector/registers, and a second stage having N selector/registers. Each of the N-1 selector/registers S1(i) in the first stage has inputs including input lanes L(j) for j going from i+1 to N. Each of the selector/registers S2(i) in the second stage has inputs including input lanes L(k) for k going from i to 0, and for selector/registers S2(i) for i less than or equal to N-2, the inputs include the output of a first stage selector/register S1(i). The outputs of the second stage selector/registers supply data selected from the respective inputs to output segment lanes. All of these selector/registers are controlled by a common select signal derived from a data path offset, and all selector/registers are clocked by a common clock.
摘要翻译：数据路径对准器将具有N字节通道的输入的数据从字节使能位传送到具有N字节通道的输出。对准器包括具有N-1个选择器/寄存器的第一级，以及具有N个选择器/寄存器的第二级。第一级中的N-1选择器/寄存器S1（i）中的每一个具有包括从i + 1到N的j的输入通道L（j）的输入。第二级中的选择器/寄存器S2（i）具有用于从i到0的k的输入通道L（k）的输入，以及对于i小于或等于N-2的选择器/寄存器S2（i），输入包括第一级选择器/寄存器S1的输出（一世）。第二级选择器/输出端的输出将从各个输入端选择的数据提供给输出段通道。所有这些选择器/寄存器由从数据路径偏移导出的公共选择信号控制，并且所有选择器/寄存器都由公共时钟计时。

4. 发明授权

US5732094A Method for automatic initiation of data transmission 失效
标题翻译：自动启动数据传输的方法
公开(公告)号：US5732094A
公开(公告)日：1998-03-24
申请号：US715253
申请日：1996-09-16
申请人： Brian Petersen , David R. Brown , W. Paul Sherer
发明人： Brian Petersen , David R. Brown , W. Paul Sherer
IPC分类号： G06F13/00 , G06F13/12 , G06F13/38 , H04L12/56 , H04L29/06 , G06F13/36
CPC分类号： H04L49/9063 , G06F13/128 , G06F13/385 , H04L29/06 , H04L47/10 , H04L47/22 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9068 , H04L49/9073 , H04L49/9078
摘要： Early initiation of transmission of data in a network interface that includes a dedicated transmit buffer is provided in a system which includes logic for transferring frames of data composed by the host computer into the transmit buffer. The amount of data of a frame which is downloaded by the host to the transmit buffer is monitored to make a threshold determination of an amount of data of the frame resident in the transmit data buffer. The network interface controller includes logic for initiating transmission of the frame when the threshold determination indicates that a sufficient portion of the frame is resident in the transmit buffer, and prior to transfer of all of the data of the frame into the transmit buffer. The monitoring logic includes a threshold store, which is programmable by the host computer for storing a threshold value. Thus, the threshold value may be set by the host system to optimize performance in a given setting.
摘要翻译：在包括专用发送缓冲器的网络接口中的数据传输的早期启动被提供在包括用于将由主机计算机组成的数据帧传送到发送缓冲器中的逻辑的系统中。监视由主机下载到发送缓冲器的帧的数据量，以对驻留在发送数据缓冲器中的帧的数据量进行阈值确定。网络接口控制器包括当阈值确定指示帧的足够部分驻留在发送缓冲器中时以及在将帧的所有数据传送到发送缓冲器之前发起帧的发送的逻辑。监视逻辑包括阈值存储，其由主计算机可编程以存储阈值。因此，阈值可由主机系统设定，以优化给定设置中的性能。

5. 发明授权

US5434872A Apparatus for automatic initiation of data transmission 失效
标题翻译：用于自动启动数据传输的装置
公开(公告)号：US5434872A
公开(公告)日：1995-07-18
申请号：US920893
申请日：1992-07-28
申请人： Brian Petersen , David R. Brown , W. Paul Sherer
发明人： Brian Petersen , David R. Brown , W. Paul Sherer
IPC分类号： G06F13/00 , G06F13/12 , G06F13/38 , H04L12/56 , H04L29/06 , H04L12/413 , H04L25/36
CPC分类号： H04L49/9063 , G06F13/128 , G06F13/385 , H04L29/06 , H04L47/10 , H04L47/22 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9068 , H04L49/9073 , H04L49/9078
摘要： Early initiation of transmission of data in a network interface that includes a dedicated transmit buffer is provided in a system which includes logic for transferring frames of data composed by the host computer into the transmit buffer. The amount of data of a frame which is downloaded by the host to the transmit buffer is monitored to make a threshold determination of an amount of data of the frame resident in the transmit data buffer. The network interface controller includes logic for initiating transmission of the frame when the threshold determination indicates that a sufficient portion of the frame is resident in the transmit buffer, and prior to transfer of all of the data of the frame into the transmit buffer. The monitoring logic includes a threshold store, which is programmable by the host computer for storing a threshold value. Thus, the threshold value may be set by the host system to optimize performance in a given setting.
摘要翻译：在包括专用发送缓冲器的网络接口中的数据传输的早期启动被提供在包括用于将由主机计算机组成的数据帧传送到发送缓冲器中的逻辑的系统中。监视由主机下载到发送缓冲器的帧的数据量，以对驻留在发送数据缓冲器中的帧的数据量进行阈值确定。网络接口控制器包括当阈值确定指示帧的足够部分驻留在发送缓冲器中时以及在将帧的所有数据传送到发送缓冲器之前发起帧的发送的逻辑。监视逻辑包括阈值存储，其由主计算机可编程以存储阈值。因此，阈值可由主机系统设定，以优化给定设置中的性能。

6. 发明授权

US5319752A Device with host indication combination 失效
标题翻译：主机指示组合的设备
公开(公告)号：US5319752A
公开(公告)日：1994-06-07
申请号：US947773
申请日：1992-09-18
申请人： Brian Petersen , Lai-Chin Lo
发明人： Brian Petersen , Lai-Chin Lo
IPC分类号： G06F13/00 , G06F13/12 , G06F13/24 , H04L12/56 , G06F13/14
CPC分类号： H04L49/901 , G06F13/128 , G06F13/24 , H04L49/90 , H04L49/9047 , H04L49/9068
摘要： Combined indication signals of data block transfers are generated by a device which reduces the number of interrupts to a host processor. The reduction in the number of interrupts enhances host system performance during data block transfers. An embodiment of the device may be a network adapter comprising network interface logic for transferring a data frame between a network and a buffer memory and host interface logic for transferring a data frame between a buffer memory and a host system. The network adapter further includes threshold logic for generating an early receive indication signal when a portion of the data frame is received. Indication combination logic delays the generation of a transfer complete interrupt to slightly before the expected occurrence of the early receive indication. The host processor is able to service both the transfer complete indication and the early receive indication in a single interrupt service routine caused by the transfer complete indication.
摘要翻译：数据块传输的组合指示信号由减少到主机处理器的中断次数的设备产生。中断数量的减少增强了数据块传输过程中的主机系统性能。设备的实施例可以是包括用于在网络和缓冲存储器之间传送数据帧的网络接口逻辑的网络适配器和用于在缓冲存储器和主机系统之间传送数据帧的主机接口逻辑。网络适配器还包括阈值逻辑，用于在接收到数据帧的一部分时产生早期接收指示信号。指示组合逻辑延迟传输完成中断的生成，稍早于预期发生的早期接收指示。主处理器能够在由传输完成指示引起的单个中断服务程序中服务传输完成指示和早期接收指示。

7. 发明授权

US5530874A Network adapter with an indication signal mask and an interrupt signal mask 失效
标题翻译：具有指示信号掩码和中断信号掩码的网络适配器
公开(公告)号：US5530874A
公开(公告)日：1996-06-25
申请号：US012561
申请日：1993-02-02
申请人： Scott A. Emery , Brian Petersen , W. Paul Sherer
发明人： Scott A. Emery , Brian Petersen , W. Paul Sherer
IPC分类号： G06F13/00 , G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： Indication and interrupt signals generated by a network adapter representing asynchronous events are managed by a host system. The network adapter includes a first mask logic for selectively disabling the indication signals from being stored in a first memory location by the host writing to a first mask register. A second mask logic which is coupled to the first memory location also selectively disables the indication signals from being stored in a second memory location creating two levels of status information. The indication signals may also be disabled from being stored in the second memory location responsive to the host writing to a second mask register. The first memory location may be read from the host in order to determine whether a network event occurred during an interrupt service routine, while interrupt means generates an interrupt signal to the host responsive to the value in the second memory location. A third level of control is provided by an internal counter which allows for automatic enabling and/or disabling of a plurality of indications and interrupts with and without explicit commands in the host driver subroutines.
摘要翻译：由代表异步事件的网络适配器产生的指示和中断信号由主机系统管理。网络适配器包括第一屏蔽逻辑，用于通过主机向第一屏蔽寄存器写入来选择性地禁用指示信号存储在第一存储器位置。耦合到第一存储器位置的第二掩模逻辑还选择性地禁止指示信号被存储在创建两级状态信息的第二存储器位置中。响应于主机向第二屏蔽寄存器的写入，也可以禁止指示信号存储在第二存储单元中。可以从主机读取第一存储器位置，以便确定在中断服务程序期间是否发生网络事件，而中断装置响应于第二存储器位置中的值产生对主机的中断信号。第三级控制由内部计数器提供，其允许在主机驱动程序子程序中使用和不使用显式命令来自动启用和/或禁用多个指示和中断。

8. 发明申请

US20110224852A1 METHODS AND SYSTEM FOR SELECTIVELY CHARGING A VEHICLE 审中-公开
标题翻译：选择充电车辆的方法和系统
公开(公告)号：US20110224852A1
公开(公告)日：2011-09-15
申请号：US12985807
申请日：2011-01-06
申请人： Elizabeth Profitt-Brown , Kelly Lee Zechel , Joseph Paul Rork , Brian Petersen , Edward Andrew Pleet , Christopher Adam Ochocinski
发明人： Elizabeth Profitt-Brown , Kelly Lee Zechel , Joseph Paul Rork , Brian Petersen , Edward Andrew Pleet , Christopher Adam Ochocinski
IPC分类号： B60L11/18 , G06F1/26
CPC分类号： H02J3/14 , B60L53/30 , B60L53/64 , B60L2240/64 , B60L2240/72 , B60L2250/18 , G06Q30/0284 , G06Q50/06 , H02J5/00 , H02J7/02 , H02J13/0062 , H02J13/0075 , H02J13/0079 , H02J2003/146 , Y02T10/7005 , Y02T10/7072 , Y02T10/7291 , Y02T90/121 , Y02T90/128 , Y02T90/14 , Y02T90/16 , Y02T90/163 , Y02T90/169 , Y04S30/14
摘要： One or more embodiments may include a method for selectively charging a vehicle. The method may include receiving at one or more computers one or more periods for charging a vehicle. The vehicle charging periods may be stored in memory. Further, pricing rates for charging the vehicle during the one or more vehicle charging periods may be received at the computer(s). Based on the one or more pricing rates and the vehicle charging periods, one or more low cost charging periods may be determined. The one or more low cost charging periods may be automatically adjusted if the one or more pricing rates change. The vehicle may be charged during at least part of the one or more low cost charging periods.
摘要翻译：一个或多个实施例可以包括用于选择性地对车辆充电的方法。该方法可以包括在一个或多个计算机处接收用于对车辆充电的一个或多个周期。车辆充电周期可以存储在存储器中。此外，在一个或多个车辆充电期间对车辆充电的定价率可以在计算机处接收。基于一个或多个定价率和车辆充电期间，可以确定一个或多个低成本充电时段。如果一个或多个定价率改变，则可以自动调整一个或多个低成本充电时段。在一个或多个低成本充电期的至少部分期间，车辆可能被充电。

9. 发明申请

US20090180391A1 NETWORK ACTIVITY ANOMALY DETECTION 审中-公开
标题翻译：网络活动异常检测
公开(公告)号：US20090180391A1
公开(公告)日：2009-07-16
申请号：US12015387
申请日：2008-01-16
申请人： Brian Petersen , Edgar Chung
发明人： Brian Petersen , Edgar Chung
IPC分类号： G06F11/00
CPC分类号： H04L43/0876 , H04L41/142 , H04L41/5022 , H04L41/5025 , H04L43/16
摘要： A method for determining whether anomalous activity exists on a network includes receiving a packet from the network, the packet including one or more fields. A classification of the packet based on the one or more fields is determined. A first counter of one or more counters associated with detecting the anomalous activity is incremented based on the classification. An activity metric associated with the one or more counters is determined based on the incrementing, wherein the activity metric is anticipated to fall within a threshold. Whether the anomalous activity exists on the network is determined based on whether the activity metric falls within the threshold.
摘要翻译：用于确定网络上是否存在异常活动的方法包括从网络接收分组，所述分组包括一个或多个字段。确定基于一个或多个字段的分组的分类。基于分类，增加与检测异常活动相关联的一个或多个计数器的第一计数器。基于递增来确定与一个或多个计数器相关联的活动度量，其中预期活动度量落入阈值内。基于活动度量是否落在阈值内，确定网络上是否存在异常活动。

10. 发明授权

US07031333B1 Reduced pin count media independent interface 失效
标题翻译：减少针数媒体独立接口
公开(公告)号：US07031333B1
公开(公告)日：2006-04-18
申请号：US09089312
申请日：1998-06-02
申请人： Stewart Findlater , James R. Rivers , David H. Yen , Brian Petersen
发明人： Stewart Findlater , James R. Rivers , David H. Yen , Brian Petersen
IPC分类号： H04J3/00
CPC分类号： H04L12/66 , H04J3/0638
摘要： A system and method are disclosed for providing a method of communicating between a media access control (MAC) layer and a physical (PHY) layer. The method includes sending a 100 MHz time-division multiplexed signal on a receive data line and sending a time-division multiplexed receive control signal on a receive control line. A 100 MHz time-division multiplexed signal is sent on a transmit data line and a time-division multiplexed transmit control signal is sent on a transmit control line.
摘要翻译：公开了一种用于提供在媒体访问控制（MAC）层和物理（PHY）层之间进行通信的方法的系统和方法。该方法包括在接收数据线上发送100MHz时分复用信号，并在接收控制线上发送时分多路复用接收控制信号。在发送数据线上发送100MHz时分多路复用信号，在发送控制线上发送时分复用发送控制信号。

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