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1. 发明授权

US5635966A Edge feed ink delivery thermal inkjet printhead structure and method of fabrication 失效
标题翻译：边缘送料墨水输送热喷墨打印头结构和制造方法
公开(公告)号：US5635966A
公开(公告)日：1997-06-03
申请号：US235610
申请日：1994-04-29
申请人： Brian J. Keefe , Steven W. Steinfield , Winthrop D. Childers , Paul H. McClelland , Kenneth E. Trueba , Duane A. Fasen , Jerome E. Beckmann , John H. Stanback , Ulrich E. Hess , James R. Hulings , Larry S. Metz , Charles E. Moore , Eldukar V. Bhaskar
发明人： Brian J. Keefe , Steven W. Steinfield , Winthrop D. Childers , Paul H. McClelland , Kenneth E. Trueba , Duane A. Fasen , Jerome E. Beckmann , John H. Stanback , Ulrich E. Hess , James R. Hulings , Larry S. Metz , Charles E. Moore , Eldukar V. Bhaskar
IPC分类号： B41J2/05 , B41J2/14 , B41J2/16 , B41J2/21
CPC分类号： B41J2/1646 , B41J2/04543 , B41J2/04546 , B41J2/0458 , B41J2/14024 , B41J2/1404 , B41J2/14072 , B41J2/14129 , B41J2/1433 , B41J2/1603 , B41J2/1623 , B41J2/1628 , B41J2/1631 , B41J2/1634 , B41J2/1635 , B41J2/1642 , B41J2/1643 , B41J2202/13
摘要： This invention provides an apparatus and method of fabrication thereof for an inkjet printhead with an improved ink flow path between an ink reservoir and vaporization chambers in an inkjet printhead. In the preferred embodiment, a barrier layer containing ink channels and vaporization chambers is located between a rectangular substrate and a nozzle member containing an array of orifices. The substrate contains two linear arrays of heater elements, and each orifice in the nozzle member is associated with a vaporization chamber and heater element. The ink channels in the barrier layer have ink entrances generally running along two opposite edges of the substrate so that ink flowing around the edges of the substrate gain access to the ink channels and to the vaporization chambers. The apparatus is fabricated without using ion implant technology.
摘要翻译：本发明提供了一种用于喷墨打印头的装置及其制造方法，其具有在墨水储存器和喷墨打印头中的蒸发室之间改进的油墨流动路径。在优选实施例中，包含油墨通道和蒸发室的阻挡层位于矩形基板和包含孔阵列的喷嘴构件之间。衬底包含两个线性阵列的加热器元件，并且喷嘴构件中的每个孔与蒸发室和加热器元件相关联。阻挡层中的墨水通道具有通常沿着基底的两个相对边缘延伸的墨水入口，使得围绕基底的边缘流动的墨水增加进入墨水通道和蒸发室。该设备是在不使用离子注入技术的情况下制造的。

2. 发明授权

US5159353A Thermal inkjet printhead structure and method for making the same 失效
标题翻译：热喷墨打印机结构及其制作方法
公开(公告)号：US5159353A
公开(公告)日：1992-10-27
申请号：US724658
申请日：1991-07-02
申请人： Duane A. Fasen , Jerome E. Beckmann , John H. Stanback , Ulrich E. Hess , James R. Hulings , Larry S. Metz , Charles E. Moore
发明人： Duane A. Fasen , Jerome E. Beckmann , John H. Stanback , Ulrich E. Hess , James R. Hulings , Larry S. Metz , Charles E. Moore
IPC分类号： B41J2/05 , B41J2/16
CPC分类号： B41J2/14129 , B41J2/1603 , B41J2/1628 , B41J2/1629 , B41J2/1631 , B41J2/1642 , B41J2/1646 , B41J2202/03 , B41J2202/13 , Y10T29/49401
摘要： An improved thermal inkjet printhead having MOSFET drive transistors incorporated therein. The gate of each MOSFET transistor is formed by applying a layer of silicon dioxide onto a silicon substrate, applying a layer of silicon nitride onto the silicon dioxide, and applying a layer of polycrystalline silicon onto the silicon nitride. Portions of the substrate surrounding the gate are oxidized, forming field oxide regions. Drain and source regions are then conventionally formed, followed by the application of a protective dielectric layer onto the field oxide, drain, source, and gate. A resistive layer is deposited on the dielectric layer and directly connected to the source, drain, and gate. A conductive layer is deposited on a portion of the resistive layer, ultimately forming both covered and uncovered regions thereof. The uncovered region functions as a heating resistor, and the covered regions function as electrical contacts to the transistor and resistor.

3. 发明授权

US5245223A CMOS latching comparator 失效
标题翻译： CMOS锁存比较器
公开(公告)号：US5245223A
公开(公告)日：1993-09-14
申请号：US853469
申请日：1992-03-17
申请人： Peter N. C. Lim , Larry S. Metz , Charles E. Moore
发明人： Peter N. C. Lim , Larry S. Metz , Charles E. Moore
IPC分类号： G01R19/165 , H03K3/356 , H03K5/08 , H03M1/34 , H03M1/74
CPC分类号： H03K3/356034 , H03K3/35613
摘要： A latching CMOS comparator method and circuit are disclosed. The comparator circuit includes a differential input stage and a latching stage. The input stage includes a differential amplifier (MP3,MP4) and a Moore Mirror load. The load includes a first cross-coupled amplifier pair (MN3,MN4), and a pair of diode-connected transistors (MN1,MN2) coupled in parallel to the first amplifier to control gain. The input stage devices are sized to provide a gain on the order of 10 to 20. The latch clock signal (CLK) is isolated from the input stage to avoid injected charge offset error. The second or latching stage includes a second cross-coupled transistor amplifier (MP7,MP8) coupled to the input stage to provide additional gain. The latch clock signal is provided to a digital switch (MP9,MP10) which controls gain in the second amplifier. The digital switch enables a second pair of diode-connected transistors (MP5,MP6) disposed in parallel to the latch stage amplifier pair, to reduce gain during sampling, for a total input referenced gain on the order of 60 during sampling. The digital switch disables the diode-connected transistors during latching, so that the second amplifier operates at maximum gain during latching. The digital switch circuitry isolates the latch clock signal from the latching nodes. After latching, the diode-connected devices speed recovery by clamping the latching node voltages. The latching nodes are coupled through inverters to an RS flip-flop circuit.
摘要翻译：公开了一种锁存CMOS比较器方法和电路。比较器电路包括差分输入级和锁存级。输入级包括差分放大器（MP3，MP4）和摩尔镜载入。负载包括第一交叉耦合放大器对（MN3，MN4）和与第一放大器并联耦合以控制增益的一对二极管连接的晶体管（MN1，MN2）。输入级装置的大小设置为提供大约10到20的增益。锁存时钟信号（CLK）与输入级隔离以避免注入电荷偏移误差。第二或锁存级包括耦合到输入级的第二交叉耦合晶体管放大器（MP7，MP8）以提供额外的增益。锁存时钟信号提供给控制第二放大器增益的数字开关（MP9，MP10）。数字开关使得与锁存级放大器对并联设置的第二对二极管连接的晶体管（MP5，MP6）可以在采样期间降低采样时的增益，从而在采样期间达到60级的总输入参考增益。数字开关在锁存期间禁用二极管连接的晶体管，以便第二放大器在锁存期间以最大增益工作。数字开关电路将锁存时钟信号与锁存节点隔离开来。锁存后，二极管连接的器件通过钳位锁存节点电压来速度恢复。锁存节点通过反相器耦合到RS触发器电路。

4. 发明授权

US5734680A Analog implementation of a partial response maximum likelihood (PRML) read channel 失效
标题翻译：部分响应最大似然（PRML）读通道的模拟实现
公开(公告)号：US5734680A
公开(公告)日：1998-03-31
申请号：US513188
申请日：1995-08-09
申请人： Charles E. Moore , Richard A. Baumgartner , Travis N. Blalock , Thomas M. Walley , Robert A. Zimmer , Rajeev Badyal , Li Ching Tsai , Larry S. Metz , Sui-Hing Leung , James S. Ignowski , Kenneth R. Stafford , Ran-Fun Chiu , Richard A. Baugh
发明人： Charles E. Moore , Richard A. Baumgartner , Travis N. Blalock , Thomas M. Walley , Robert A. Zimmer , Rajeev Badyal , Li Ching Tsai , Larry S. Metz , Sui-Hing Leung , James S. Ignowski , Kenneth R. Stafford , Ran-Fun Chiu , Richard A. Baugh
IPC分类号： G11B5/09 , G11B20/10 , H04L5/12
CPC分类号： G11B5/09 , G11B20/10009
摘要： An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.
摘要翻译：提供了利用高性能模拟延迟线的模拟，完全集成的部分响应最大似然（PRML）读取通道，模拟自适应均衡器和模拟维特比检测器，从而节省空间，提高性能并降低功耗。对于在读操作中使用的信号检测和重建，部分响应最大似然（PRML）读通道包括耦合到低通滤波器的可变增益放大器，用于输入到自适应模拟均衡器。自适应模拟均衡器包括模拟延迟线和模拟前馈均衡器（FFE）。模拟维特比检测器采用最大似然序列估计（MLSE）技术来执行信号检测功能。解码器/解扰器产生最终的重构信号。部分响应最大似然（PRML）读通道的模拟实现还包括耦合到写预补偿电路的加扰器/编码器，以输出到单独的写头。

5. 发明授权

US5302863A CMOS peak amplitude detector 失效
标题翻译： CMOS峰值检波器
公开(公告)号：US5302863A
公开(公告)日：1994-04-12
申请号：US11028
申请日：1993-01-29
申请人： Thomas M. Walley , Larry S. Metz , Charles E. Moore
发明人： Thomas M. Walley , Larry S. Metz , Charles E. Moore
IPC分类号： G01R19/04 , G11C27/00 , G11C27/02 , H03K5/1532 , H03K5/153
CPC分类号： H03K5/1532 , G01R19/04 , G11C27/00 , G11C27/026
摘要： A fully-integrated CMOS peak detector stores the peak amplitude of an input signal using an on-chip storage capacitor. The fully-integrated CMOS peak detector includes a delay buffer, a transfer gate and a comparator. A discharge controller is used to step-down the peak amplitude stored on the on-chip storage capacitor some predetermined amount. The discharge controller includes a switched capacitor circuit which is placed in series with the storage capacitor such that the two capacitors act as a capacitive voltage divider to produce a predictable fraction of the acquired peak amplitude. Multiple peaks can be determined and/or stored by using multiple fully-integrated CMOS peak detectors in conjunction with a single comparator. A multiplexer is used in this configuration to control the multiple peak detectors.
摘要翻译：全集成CMOS峰值检测器使用片上存储电容器存储输入信号的峰值幅度。完全集成的CMOS峰值检测器包括延迟缓冲器，传输门和比较器。放电控制器用于降低存储在片上存储电容器上的峰值幅度一定的量。放电控制器包括与存储电容器串联放置的开关电容器电路，使得两个电容器用作电容分压器以产生所获取的峰值幅度的可预测分数。可以通过结合单个比较器使用多个完全集成的CMOS峰值检测器来确定和/或存储多个峰。在该配置中使用多路复用器来控制多个峰值检测器。

6. 发明授权

US5247299A Successive approximation A/D converter correcting for charge injection offset 失效
标题翻译：逐次逼近A / D转换器校正电荷注入偏移
公开(公告)号：US5247299A
公开(公告)日：1993-09-21
申请号：US892103
申请日：1992-06-02
申请人： Peter N. C. Lim , Larry S. Metz
发明人： Peter N. C. Lim , Larry S. Metz
IPC分类号： H03M1/10 , H03M1/06 , H03M1/38 , H03M1/46
CPC分类号： H03M1/0607 , H03M1/46
摘要： In a successive-approximation analog-to-digital conversion application, charge injection offset at the sample input of the comparator resulting from the changing DAC reference voltage, is converted to a fixed, systematic offset. In the comparator differential input stage, the reference or driven input device is turned off during a sample time, prior to beginning the conversion process, so that substantially all of a predetermined bias current flows in the sample side of the comparator. Given this initial condition, the change in input voltage through conversion is a fixed function of the device geometry, bias current and gain, independent of the sample voltage, and therefore may be calibrated out of the system. The comparator input stage includes a differential pair of MOS transistors. A CMOS transmission gate is coupled between the DAC output and the reference comparator input. A switch transistor is coupled between the reference input, i.e. the gate of M2, and Vdd for biasing off M2 during sample time. Transmission gate and switch transistor are controlled by a binary control signal "sample/convert" to turn M2 off during a sample time, and to couple the DAC output to the reference input during convert time.
摘要翻译：在逐次逼近模数转换应用中，由DAC参考电压变化引起的比较器采样输入端的电荷注入偏移被转换为固定的系统偏移。在比较器差分输入级中，参考或驱动输入器件在采样时间之前，在开始转换处理之前被关断，使得基本上所有的预定偏置电流都流过比较器的采样侧。给定该初始条件，通过转换的输入电压的变化是器件几何形状，偏置电流和增益的固定函数，与采样电压无关，因此可以从系统中校准。比较器输入级包括差分MOS晶体管对。 CMOS输出门耦合在DAC输出和参考比较器输入之间。开关晶体管耦合在参考输入端，即M2的栅极和Vdd之间，用于在采样时间期间偏置M2。传输门和开关晶体管由二进制控制信号“采样/转换”控制，以在采样时间内关断M2，并在转换时间期间将DAC输出耦合到参考输入。

7. 发明授权

US5452171A Electrostatic discharge protection circuit for integrated circuits 失效
标题翻译：用于集成电路的静电放电保护电路
公开(公告)号：US5452171A
公开(公告)日：1995-09-19
申请号：US149858
申请日：1993-11-10
申请人： Larry S. Metz , Gordon W. Motley
发明人： Larry S. Metz , Gordon W. Motley
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/08 , H01L27/092 , H02H3/00 , H02H9/04 , H03K19/003 , H01L29/06
CPC分类号： H01L27/0262 , H01L27/0251 , H02H9/046 , H01L2924/0002 , H02H3/006
摘要： An ESD protection circuit that uses the well-known SCR latchup effect present in CMOS processes to divert the ESD current pulse away from sensitive circuit structures. The circuit uses an inverter trigger device, with a voltage divider on its output, to control the amount of voltage necessary to cause latchup. This feature enables the SCR to absorb a high current pulse on the CMOS pad structures caused by an ESD event, while also preventing the circuit from latching when an ordinary CMOS voltage is applied to the pad while the circuit being protected is unpowered. The circuit insures that the SCR will latch independent of breakdown effects, while also allowing the threshold voltage at which latchup occurs to be adjusted into the circuit by varying the sizes of two FETS used as the voltage divider.
摘要翻译：使用CMOS工艺中存在的众所周知的SCR闭锁效应的ESD保护电路将ESD电流脉冲转移离开敏感电路结构。该电路使用一个逆变器触发装置，在其输出端带有一个分压器，以控制引起闭锁所需的电压量。该特征使得SCR能够吸收由ESD事件引起的CMOS焊盘结构上的高电流脉冲，同时还防止当普通CMOS电压施加到焊盘时电路锁定，同时保护电路未被供电。该电路确保SCR将独立于击穿效应锁存，同时还允许通过改变用作分压器的两个FET的尺寸将闭锁发生的阈值电压调整到电路中。

8. 发明授权

US07254505B2 Method and apparatus for calibrating delay lines 失效
标题翻译：用于校准延迟线的方法和装置
公开(公告)号：US07254505B2
公开(公告)日：2007-08-07
申请号：US11170207
申请日：2005-06-29
申请人： Ronnie E. Owens , Theodore G. Rossin , Larry S. Metz
发明人： Ronnie E. Owens , Theodore G. Rossin , Larry S. Metz
IPC分类号： H03L7/06
CPC分类号： G01R31/31725 , G01R31/3191 , H03K2005/0011
摘要： A delay line (DL) circuit used to generate test pattern waveforms has a pulse generating circuit that is used during calibration to generate a pulse signal upon receiving a signal edge. A delay line of the DL circuit receives the pulse signal and delays the pulse signal by a selected time delay. A feedback loop of the DL circuit feeds the delayed pulse signal output from the delay line back to the input of the pulse generating circuit. Receipt of an edge of the fed back pulse signal at the input of the pulse generating circuit causes the pulse generating circuit to generate another pulse signal. The delayed pulse signal output from the delay line can be input to a counter that generates a counter value that is based on the period of oscillation of the delayed pulse signal.
摘要翻译：用于产生测试图形波形的延迟线（DL）电路具有在校准期间使用的脉冲发生电路，以在接收到信号边缘时产生脉冲信号。 DL电路的延迟线接收脉冲信号并将脉冲信号延迟选定的时间延迟。 DL电路的反馈环路将从延迟线输出的延迟脉冲信号馈送回脉冲发生电路的输入端。在脉冲发生电路的输入处接收反馈脉冲信号的边沿使脉冲发生电路产生另一个脉冲信号。从延迟线输出的延迟脉冲信号可以输入到产生基于延迟脉冲信号的振荡周期的计数器值的计数器。

9. 发明授权

US5447051A Method and apparatus for testing a piezoelectric force sensor 失效
标题翻译：用于测试压电力传感器的方法和装置
公开(公告)号：US5447051A
公开(公告)日：1995-09-05
申请号：US102597
申请日：1993-08-05
申请人： D. Mitchel Hanks , Larry S. Metz
发明人： D. Mitchel Hanks , Larry S. Metz
IPC分类号： G01L25/00 , G01P15/09 , G01P21/00 , G01R29/22 , G01P15/08
CPC分类号： G01P15/0922 , G01P21/00
摘要： A test system for a piezoelectric element per se or a piezoelectric element in a physical system, which is subject to forces which deform the piezoelectric element, couples an electrical pulse to the piezoelectric element sufficient to stress the element and induce mechanical ringing upon pulse removal. The ringing electrical signal developed by the piezoelectric element characterizes the functionality of the piezoelectric element. A response circuit which is responsive to the ringing electrical signal provides an electrical signal indicative of the functional condition of the piezoelectric element. The electrical signal is peak detected. The peak detected voltage is compared with a reference voltage to provide an indication of the functionality of the piezoelectric element.
摘要翻译：用于压电元件本身的测试系统或物理系统中的受压力使压电元件变形的压电元件的测试系统将电脉冲耦合到压电元件，足以在脉冲去除时对元件施加应力并引起机械振铃。由压电元件开发的振铃电信号表征了压电元件的功能。响应于振铃电信号的响应电路提供表示压电元件的功能状态的电信号。电信号是峰值检测。将峰值检测电压与参考电压进行比较，以提供压电元件的功能性的指示。

10. 发明授权

US5400202A Electrostatic discharge protection circuit for integrated circuits 失效
标题翻译：用于集成电路的静电放电保护电路
公开(公告)号：US5400202A
公开(公告)日：1995-03-21
申请号：US898997
申请日：1992-06-15
申请人： Larry S. Metz , Gordon Motley , George Rieck
发明人： Larry S. Metz , Gordon Motley , George Rieck
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H02H3/00 , H02H9/04
CPC分类号： H01L27/0262 , H01L27/0251 , H02H9/046 , H01L2924/0002 , H02H3/006
摘要： A circuit for protecting integrated circuits from electrostatic discharge by using SCR latchup to divert the ESD current pulse away from sensitive circuit structures. The SCR structure of the invention includes a trigger circuit having an NMOS triggering transistor for activating the SCR when an ESD event occurs on an input/output pad of the integrated circuit being protected. The ESD event on the input/output pad of the integrated circuit is detected by a circuit which applies a trigger voltage to the NMOS triggering transistor to initiate latchup of the SCR independent of junction breakdown of the NMOS triggering transistor. The trigger voltage is generated by an inverter trigger or a capacitor trigger powered by the ESD event so as to trigger SCR latchup so long as the integrated circuit is not powered up (V.sub.DD is low). The SCR of the invention may also have a floating well whereby the well resistor R.sub.w of the SCR is replaced by a CMOS device which inhibits forward biasing of the pnp base of the SCR when V.sub.DD is high but allows small currents to forward bias the pnp base when V.sub.DD is low. The NMOS trigger FET of the invention also may be isolated from the substrate containing the SCR so as to further decrease the effects of junction breakdown conditions on the latchup of the SCR.
摘要翻译：通过使用SCR闭锁来保护集成电路免受静电放电的电路，用于将ESD电流脉冲转移离开敏感电路结构。本发明的SCR结构包括具有NMOS触发晶体管的触发电路，用于在被保护的集成电路的输入/输出焊盘上发生ESD事件时激活SCR。集成电路的输入/输出焊盘上的ESD事件由电路检测，该电路向NMOS触发晶体管施加触发电压以启动SCR的闭锁，而不管NMOS触发晶体管的结击穿。触发电压由逆变器触发或由ESD事件供电的电容触发产生，以便只要集成电路未上电（VDD为低电平）就触发SCR闭锁。本发明的SCR还可以具有浮置阱，由此SCR的阱电阻器Rw被CMOS器件替代，当VDD为高电平时，该器件阻止SCR的pnp基极的正向偏置，但允许小电流向pnp基极当VDD为低电平时。本发明的NMOS触发FET也可以与含有SCR的衬底隔离，以进一步降低结击穿条件对SCR闭锁的影响。

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