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1. 发明授权

US5247299A Successive approximation A/D converter correcting for charge injection offset 失效
标题翻译：逐次逼近A / D转换器校正电荷注入偏移
公开(公告)号：US5247299A
公开(公告)日：1993-09-21
申请号：US892103
申请日：1992-06-02
申请人： Peter N. C. Lim , Larry S. Metz
发明人： Peter N. C. Lim , Larry S. Metz
IPC分类号： H03M1/10 , H03M1/06 , H03M1/38 , H03M1/46
CPC分类号： H03M1/0607 , H03M1/46
摘要： In a successive-approximation analog-to-digital conversion application, charge injection offset at the sample input of the comparator resulting from the changing DAC reference voltage, is converted to a fixed, systematic offset. In the comparator differential input stage, the reference or driven input device is turned off during a sample time, prior to beginning the conversion process, so that substantially all of a predetermined bias current flows in the sample side of the comparator. Given this initial condition, the change in input voltage through conversion is a fixed function of the device geometry, bias current and gain, independent of the sample voltage, and therefore may be calibrated out of the system. The comparator input stage includes a differential pair of MOS transistors. A CMOS transmission gate is coupled between the DAC output and the reference comparator input. A switch transistor is coupled between the reference input, i.e. the gate of M2, and Vdd for biasing off M2 during sample time. Transmission gate and switch transistor are controlled by a binary control signal "sample/convert" to turn M2 off during a sample time, and to couple the DAC output to the reference input during convert time.
摘要翻译：在逐次逼近模数转换应用中，由DAC参考电压变化引起的比较器采样输入端的电荷注入偏移被转换为固定的系统偏移。在比较器差分输入级中，参考或驱动输入器件在采样时间之前，在开始转换处理之前被关断，使得基本上所有的预定偏置电流都流过比较器的采样侧。给定该初始条件，通过转换的输入电压的变化是器件几何形状，偏置电流和增益的固定函数，与采样电压无关，因此可以从系统中校准。比较器输入级包括差分MOS晶体管对。 CMOS输出门耦合在DAC输出和参考比较器输入之间。开关晶体管耦合在参考输入端，即M2的栅极和Vdd之间，用于在采样时间期间偏置M2。传输门和开关晶体管由二进制控制信号“采样/转换”控制，以在采样时间内关断M2，并在转换时间期间将DAC输出耦合到参考输入。

2. 发明授权

US5245223A CMOS latching comparator 失效
标题翻译： CMOS锁存比较器
公开(公告)号：US5245223A
公开(公告)日：1993-09-14
申请号：US853469
申请日：1992-03-17
申请人： Peter N. C. Lim , Larry S. Metz , Charles E. Moore
发明人： Peter N. C. Lim , Larry S. Metz , Charles E. Moore
IPC分类号： G01R19/165 , H03K3/356 , H03K5/08 , H03M1/34 , H03M1/74
CPC分类号： H03K3/356034 , H03K3/35613
摘要： A latching CMOS comparator method and circuit are disclosed. The comparator circuit includes a differential input stage and a latching stage. The input stage includes a differential amplifier (MP3,MP4) and a Moore Mirror load. The load includes a first cross-coupled amplifier pair (MN3,MN4), and a pair of diode-connected transistors (MN1,MN2) coupled in parallel to the first amplifier to control gain. The input stage devices are sized to provide a gain on the order of 10 to 20. The latch clock signal (CLK) is isolated from the input stage to avoid injected charge offset error. The second or latching stage includes a second cross-coupled transistor amplifier (MP7,MP8) coupled to the input stage to provide additional gain. The latch clock signal is provided to a digital switch (MP9,MP10) which controls gain in the second amplifier. The digital switch enables a second pair of diode-connected transistors (MP5,MP6) disposed in parallel to the latch stage amplifier pair, to reduce gain during sampling, for a total input referenced gain on the order of 60 during sampling. The digital switch disables the diode-connected transistors during latching, so that the second amplifier operates at maximum gain during latching. The digital switch circuitry isolates the latch clock signal from the latching nodes. After latching, the diode-connected devices speed recovery by clamping the latching node voltages. The latching nodes are coupled through inverters to an RS flip-flop circuit.
摘要翻译：公开了一种锁存CMOS比较器方法和电路。比较器电路包括差分输入级和锁存级。输入级包括差分放大器（MP3，MP4）和摩尔镜载入。负载包括第一交叉耦合放大器对（MN3，MN4）和与第一放大器并联耦合以控制增益的一对二极管连接的晶体管（MN1，MN2）。输入级装置的大小设置为提供大约10到20的增益。锁存时钟信号（CLK）与输入级隔离以避免注入电荷偏移误差。第二或锁存级包括耦合到输入级的第二交叉耦合晶体管放大器（MP7，MP8）以提供额外的增益。锁存时钟信号提供给控制第二放大器增益的数字开关（MP9，MP10）。数字开关使得与锁存级放大器对并联设置的第二对二极管连接的晶体管（MP5，MP6）可以在采样期间降低采样时的增益，从而在采样期间达到60级的总输入参考增益。数字开关在锁存期间禁用二极管连接的晶体管，以便第二放大器在锁存期间以最大增益工作。数字开关电路将锁存时钟信号与锁存节点隔离开来。锁存后，二极管连接的器件通过钳位锁存节点电压来速度恢复。锁存节点通过反相器耦合到RS触发器电路。

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