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1. 发明申请

US20090141571A1 Method and Apparatus for Initialization of Read Latency Tracking Circuit in High-Speed DRAM 有权
标题翻译：用于在高速DRAM中初始化读延迟跟踪电路的方法和装置
公开(公告)号：US20090141571A1
公开(公告)日：2009-06-04
申请号：US12329779
申请日：2008-12-08
申请人： James Brian Johnson , Brent Keeth , Feng Dan Lin
发明人： James Brian Johnson , Brent Keeth , Feng Dan Lin
IPC分类号： G11C7/00 , G11C8/18 , G11C8/00
CPC分类号： G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4072 , G11C11/4076 , G11C2207/2254 , H03L7/0812 , H03L7/095
摘要： A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing.
摘要翻译：控制来自存储器件的数据输出的方法包括从外部时钟信号导出读时钟和用于操作存储单元阵列的控制时钟，读时钟和控制时钟均由时钟脉冲组成。值被预加载到位于读时钟域中的第一计数器中的一个或两者，位于控制时钟域中的第二计数器，使得两个计数器之间的启动计数的差值等于列地址选通延迟（L）减去同步（SP）开销。产生起始信号，用于开始产生第一计数器中的读取时钟脉冲的运行计数。启动信号到第二计数器的输入被延迟，以延迟启动控制时钟脉冲的运行计数。响应于读取命令来保持第二计数器的值。将第二计数器的保持值与第一计数器的运行计数进行比较; 并且响应于比较，从存储器件输出具有读时钟信号的数据。

2. 发明授权

US07480203B2 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM 有权
公开(公告)号：US07480203B2
公开(公告)日：2009-01-20
申请号：US12072109
申请日：2008-02-22
申请人： James Brian Johnson , Brent Keeth , Feng (Dan) Lin
发明人： James Brian Johnson , Brent Keeth , Feng (Dan) Lin
IPC分类号： G11C8/00 , H03L7/06
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2254 , H03L7/0812 , H03L7/095
摘要： A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock. The input of the start signal to a second counter is delayed to delay the initiation of a running count of the control clock pulses. The delay, which may be expressed as an integer number of clock cycles, may be equal to an input/output delay of the memory device. The method may be modified by inputting the start signal to an offset counter before initiating the production of the running count of the read clock pulses in the first counter. The offset counter may be loaded with a value equal to a programmed latency less a synchronization overhead. Once the running counts are initiated, each time a read command is received, a then current value of the running count of control clock pulses from the second counter is latched or held. The held value is compared to the running count of read clock pulses from the first counter, with the read clock signal being used to output data in response to the comparison. Apparatus for implementing the disclosed methods are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

3. 发明授权

US07355922B2 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM 有权
公开(公告)号：US07355922B2
公开(公告)日：2008-04-08
申请号：US11429856
申请日：2006-05-08
申请人： James Brian Johnson , Brent Keeth , Feng (Dan) Lin
发明人： James Brian Johnson , Brent Keeth , Feng (Dan) Lin
IPC分类号： G11C8/00 , H03L7/06
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2254 , H03L7/0812 , H03L7/095
摘要： A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock. The input of the start signal to a second counter is delayed to delay the initiation of a running count of the control clock pulses. The delay, which may be expressed as an integer number of clock cycles, may be equal to an input/output delay of the memory device. The method may be modified by inputting the start signal to an offset counter before initiating the production of the running count of the read clock pulses in the first counter. The offset counter may be loaded with a value equal to a programmed latency less a synchronization overhead. Once the running counts are initiated, each time a read command is received, a then current value of the running count of control clock pulses from the second counter is latched or held. The held value is compared to the running count of read clock pulses from the first counter, with the read clock signal being used to output data in response to the comparison. Apparatus for implementing the disclosed methods are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

4. 发明申请

US20080225630A1 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM 有权
公开(公告)号：US20080225630A1
公开(公告)日：2008-09-18
申请号：US12072109
申请日：2008-02-22
申请人： James Brian Johnson , Brent Keeth , Feng Dan Lin
发明人： James Brian Johnson , Brent Keeth , Feng Dan Lin
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2254 , H03L7/0812 , H03L7/095
摘要： A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock. The input of the start signal to a second counter is delayed to delay the initiation of a running count of the control clock pulses. The delay, which may be expressed as an integer number of clock cycles, may be equal to an input/output delay of the memory device. The method may be modified by inputting the start signal to an offset counter before initiating the production of the running count of the read clock pulses in the first counter. The offset counter may be loaded with a value equal to a programmed latency less a synchronization overhead. Once the running counts are initiated, each time a read command is received, a then current value of the running count of control clock pulses from the second counter is latched or held. The held value is compared to the running count of read clock pulses from the first counter, with the read clock signal being used to output data in response to the comparison. Apparatus for implementing the disclosed methods are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

5. 发明授权

US07065001B2 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM 有权
公开(公告)号：US07065001B2
公开(公告)日：2006-06-20
申请号：US10910838
申请日：2004-08-04
申请人： James Brian Johnson , Brent Keeth , Feng (Dan) Lin
发明人： James Brian Johnson , Brent Keeth , Feng (Dan) Lin
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2254 , H03L7/0812 , H03L7/095
摘要： A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock. The input of the start signal to a second counter is delayed to delay the initiation of a running count of the control clock pulses. The delay, which may be expressed as an integer number of clock cycles, may be equal to an input/output delay of the memory device. The method may be modified by inputting the start signal to an offset counter before initiating the production of the running count of the read clock pulses in the first counter. The offset counter may be loaded with a value equal to a programmed latency less a synchronization overhead. Once the running counts are initiated, each time a read command is received, a then current value of the running count of control clock pulses from the second counter is latched or held. The held value is compared to the running count of read clock pulses from the first counter, with the read clock signal being used to output data in response to the comparison. Apparatus for implementing the disclosed methods are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

6. 发明授权

US07660187B2 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM 有权
标题翻译：用于在高速DRAM中初始化读延迟跟踪电路的方法和装置
公开(公告)号：US07660187B2
公开(公告)日：2010-02-09
申请号：US12329779
申请日：2008-12-08
申请人： James Brian Johnson , Brent Keeth , Feng Dan Lin
发明人： James Brian Johnson , Brent Keeth , Feng Dan Lin
IPC分类号： G11C8/00 , H03L7/06
CPC分类号： G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4072 , G11C11/4076 , G11C2207/2254 , H03L7/0812 , H03L7/095
摘要： A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing.
摘要翻译：控制来自存储器件的数据输出的方法包括从外部时钟信号导出读时钟和用于操作存储单元阵列的控制时钟，读时钟和控制时钟均由时钟脉冲组成。值被预加载到位于读时钟域中的第一计数器中的一个或两者，位于控制时钟域中的第二计数器，使得两个计数器之间的启动计数的差值等于列地址选通延迟（L）减去同步（SP）开销。产生起始信号，用于开始产生第一计数器中的读取时钟脉冲的运行计数。启动信号到第二计数器的输入被延迟，以延迟启动控制时钟脉冲的运行计数。响应于读取命令来保持第二计数器的值。将第二计数器的保持值与第一计数器的运行计数进行比较; 并且响应于比较，从存储器件输出具有读时钟信号的数据。

7. 发明授权

US07404124B2 On-chip sampling circuit and method 失效
标题翻译：片上采样电路及方法
公开(公告)号：US07404124B2
公开(公告)日：2008-07-22
申请号：US11712040
申请日：2007-02-28
申请人： Chris Martin , James Brian Johnson , Troy Manning , Brent Keeth
发明人： Chris Martin , James Brian Johnson , Troy Manning , Brent Keeth
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G11C29/1201
摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.
摘要翻译：通过寻址电路，采样电路可以在封装/封装的芯片上选择唯一的内部节点/信号，以输出到一个或多个驱动器。在目标节点处可用的选定信号通过选择电路指向输出引脚，或直接指向输出引脚。在优选模式中，用于选择唯一节点的解码电路串联连接，允许大量的信号可用于分析，而不会对电路布局造成很大影响。由于与摘要相关的规则，本摘要不应用于索赔的构建。

8. 发明授权

US07412634B2 On-chip sampling circuit and method 失效
公开(公告)号：US07412634B2
公开(公告)日：2008-08-12
申请号：US11712041
申请日：2007-02-28
申请人： Chris Martin , James Brian Johnson , Troy Manning , Brent Keeth
发明人： Chris Martin , James Brian Johnson , Troy Manning , Brent Keeth
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G11C29/1201
摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

9. 发明授权

US07251762B2 On-chip sampling circuit and method 有权
标题翻译：片上采样电路及方法
公开(公告)号：US07251762B2
公开(公告)日：2007-07-31
申请号：US11109535
申请日：2005-04-19
申请人： Chris Martin , James Brian Johnson , Troy Manning , Brent Keeth
发明人： Chris Martin , James Brian Johnson , Troy Manning , Brent Keeth
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G11C29/1201
摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout.
摘要翻译：通过寻址电路，采样电路可以在封装/封装的芯片上选择唯一的内部节点/信号，以输出到一个或多个驱动器。在目标节点处可用的选定信号通过选择电路指向输出引脚，或直接指向输出引脚。在优选模式中，用于选择唯一节点的解码电路串联连接，允许大量的信号可用于分析，而不会对电路布局造成很大影响。

10. 发明授权

US07881149B2 Write latency tracking using a delay lock loop in a synchronous DRAM 有权
标题翻译：使用同步DRAM中的延迟锁定环来写入延迟跟踪
公开(公告)号：US07881149B2
公开(公告)日：2011-02-01
申请号：US12551876
申请日：2009-09-01
申请人： James Brian Johnson , Feng Lin , Brent Keeth
发明人： James Brian Johnson , Feng Lin , Brent Keeth
IPC分类号： G11C8/00
CPC分类号： G11C29/50 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/50012
摘要： A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL. By backing the distribution delay out of system clock as sent to the deserializers, the write valid signal is effectively synchronized with the write strobe, with the effect that data will be passed out of the deserializer circuitry to the memory array on time and consistent with the programmed write latency.
摘要翻译：公开了一种用于在SDRAM中改进写延迟跟踪的方法和电路。在一个实施例中，在写入路径的命令部分中使用延迟锁定环，并且接收系统时钟作为其参考输入。 DLL包括建模延迟，其将内部写入有效信号的传输延迟和系统时钟分布建模到写入路径的数据路径部分中的解串行器，否则由间歇性断言的写入选通信号控制。随着系统时钟（Clk）的输入分配延迟和设计匹配的写选通（WS），分布式系统时钟和写有效信号通过参考系统时钟的DLL延迟与WS分配路径同步输入到DLL。通过将分发延迟从发送到解串器的系统时钟中提取出来，写入有效信号与写入选通有效地同步，其影响是数据将及时从解串器电路传送到存储器阵列，并与编程写延迟。

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