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1. 发明授权

US5664060A Message management methods and apparatus 失效
标题翻译：消息管理方法和设备
公开(公告)号：US5664060A
公开(公告)日：1997-09-02
申请号：US186793
申请日：1994-01-25
申请人： Boyce W. Jarrett , Bindiganavale S. Nataraj , Sakhawat M. Khan
发明人： Boyce W. Jarrett , Bindiganavale S. Nataraj , Sakhawat M. Khan
IPC分类号： G06F3/08 , G11C27/00 , G10L3/00 , H04M1/64
CPC分类号： G11C27/005
摘要： Message management methods and apparatus for the storage and selective playback, erase and other manipulation of messages such as voice messages in a voice message system are disclosed. The devices of the invention include analog signal sample and analog storage capabilities whereby messages may be stored in one or more message segment storage locations. A register stack in each device keeps track of the message number associated with the message segment stored in the respective message segment location so that message segments associated with a particular message may be located in sequence for seamless playback of the entire message. Message segment storage locations available for storing new messages may be identified by a flag identifying the same, such as by an otherwise unused message number stored in the associated stack register. Each device includes the capability of cascading with identical devices so as to extend the total record and playback time available. Other aspects of the invention, including other features and capabilities of the devices and details of the method are disclosed.
摘要翻译：公开了用于在语音消息系统中存储和选择性重放，擦除和其他操作诸如语音消息的消息的消息管理方法和装置。本发明的设备包括模拟信号样本和模拟存储能力，从而可以将消息存储在一个或多个消息段存储位置中。每个设备中的寄存器堆栈跟踪与存储在相应消息段位置中的消息段相关联的消息号，使得与特定消息相关联的消息段可以按顺序被定位，以便整个消息的无缝重放。可用于存储新消息的消息段存储位置可以由标识其的标志来标识，诸如通过存储在相关联的堆栈寄存器中的另外未使用的消息号来标识。每个设备包括与相同设备级联的功能，以便扩展总记录和播放时间。公开了本发明的其它方面，包括装置的其他特征和能力以及该方法的细节。

2. 发明授权

US08031501B1 Segmented content addressable memory device having pipelined compare operations 有权
标题翻译：具有流水线比较操作的分段内容可寻址存储器设备
公开(公告)号：US08031501B1
公开(公告)日：2011-10-04
申请号：US12909714
申请日：2010-10-21
申请人： Bindiganavale S. Nataraj , Chetan Deshpande , Vinay Iyengar , Sandeep Khanna
发明人： Bindiganavale S. Nataraj , Chetan Deshpande , Vinay Iyengar , Sandeep Khanna
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/00
摘要： Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on a detected matching condition of another cell block. By selectively enabling cell blocks during search operations only when needed, energy consumption is reduced. Selectively enabling a cell block includes selectively pre-charging match lines to the cell block, selectively enabling word lines to the cell block, and selectively enabling comparand line to the cell block. In accordance with certain embodiments, the CAM device is configurable to perform search operations in a pipelined manner. Accordingly, the CAM device is capable of performing multiple search operations simultaneously.
摘要翻译：本实施例描述具有分段CAM阵列的CAM设备。 CAM阵列或单元块的每个段包括一行或多行CAM单元。基于检测到的另一个单元块的匹配条件，在搜索操作期间，CAM阵列中的一个或多个单元块被选择性地使能。通过在搜索操作期间仅在需要时选择性地使能单元块，能量消耗降低。选择性地启用单元块包括选择性地将匹配线预充电到单元块，选择性地使得字线到单元块，以及选择性地使能与单元块的比较线。根据某些实施例，CAM设备可配置为以流水线方式执行搜索操作。因此，CAM设备能够同时执行多个搜索操作。

3. 发明授权

US07920398B1 Adaptive match line charging 有权
标题翻译：自适应匹配线充电
公开(公告)号：US07920398B1
公开(公告)日：2011-04-05
申请号：US12887267
申请日：2010-09-21
申请人： Sandeep Khanna , Bindiganavale S. Nataraj , Chetan Deshpande , Vinay Iyengar
发明人： Sandeep Khanna , Bindiganavale S. Nataraj , Chetan Deshpande , Vinay Iyengar
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C7/12
摘要： A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and a pre-charge circuit. The detector circuit detects a voltage of the match line and generates a feedback signal based on the detected match line voltage. The pre-charge circuit adaptively charges the match line in response to the feedback signal.
摘要翻译：一种具有任意行数的内容可寻址存储器（CAM）器件，每行包括连接到多个CAM单元的匹配线，匹配线检测器电路和预充电电路。检测器电路检测匹配线的电压，并基于检测到的匹配线电压产生反馈信号。预充电电路响应于反馈信号自适应地对匹配线进行充电。

4. 发明授权

US06906937B1 Bit line control circuit for a content addressable memory 有权
标题翻译：位线控制电路，用于内容可寻址存储器
公开(公告)号：US06906937B1
公开(公告)日：2005-06-14
申请号：US10394983
申请日：2003-03-21
申请人： Bindiganavale S. Nataraj
发明人： Bindiganavale S. Nataraj
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： A bit line control circuit is coupled between a bit line of an associated Content Addressable Memory (CAM). Array and a supply voltage. The bit line control circuit adjusts the charge current for the bit line in response to a bit line control signal. For some embodiments, the bit line control circuit includes a dynamic component and a static component to control the bit line.
摘要翻译：位线控制电路耦合在相关联的内容可寻址存储器（CAM）的位线之间。阵列和电源电压。位线控制电路响应于位线控制信号调整位线的充电电流。对于一些实施例，位线控制电路包括用于控制位线的动态分量和静态分量。

5. 发明授权

US06714430B1 Content addressable memory having column redundancy 有权
标题翻译：内容可寻址内存，具有列冗余
公开(公告)号：US06714430B1
公开(公告)日：2004-03-30
申请号：US10143051
申请日：2002-05-10
申请人： Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
发明人： Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
IPC分类号： G11C1500
CPC分类号： G11C29/846 , G11C15/00 , G11C29/848
摘要： A content addressable memory (CAM) having a main array including a plurality of columns of CAM cells, a spare column of CAM cells selectable to functionally replace a defective column of CAM cells in the main array, a steering circuit for steering data corresponding to the defective column to the spare column, and a global mask circuit for masking the defective column during a compare operation.
摘要翻译：一种内容可寻址存储器（CAM），其具有包括多个CAM单元列的主阵列，可选择功能地替换主阵列中的CAM单元的缺陷列的CAM单元的备用列，用于转向对应于缺陷列到备用列，以及全局掩模电路，用于在比较操作期间屏蔽缺陷列。

6. 发明授权

US06567340B1 Memory storage cell based array of counters 有权
标题翻译：内存存储单元阵列的计数器
公开(公告)号：US06567340B1
公开(公告)日：2003-05-20
申请号：US09846513
申请日：2001-04-30
申请人： Bindiganavale S. Nataraj , Varadarajan Srinivasan , Sandeep Khanna
发明人： Bindiganavale S. Nataraj , Varadarajan Srinivasan , Sandeep Khanna
IPC分类号： G11C800
CPC分类号： G11C8/04 , G11C15/04 , H03K3/356139 , H03K23/56
摘要： A multi-counter based system having a counter array. Each counter of the array having a memory cell. The system also includes an address decoder coupled to the counter array to select at least one of the memory cells within the counter array and read/write circuitry coupled to the counter array to pass data with the counter array.
摘要翻译：一种具有计数器阵列的多计数器系统。阵列的每个计数器具有存储单元。该系统还包括耦合到计数器阵列的地址解码器，以选择计数器阵列内的至少一个存储单元和耦合到计数器阵列的读/写电路，以便与计数器阵列传递数据。

7. 发明授权

US06445628B1 Row redundancy in a content addressable memory 有权
标题翻译：内容可寻址内存中的行冗余
公开(公告)号：US06445628B1
公开(公告)日：2002-09-03
申请号：US09886235
申请日：2001-06-18
申请人： Jose Pio Pereira , Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
发明人： Jose Pio Pereira , Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
IPC分类号： G11C700
CPC分类号： G11C15/04 , G11C15/00 , G11C29/785 , G11C29/816
摘要： A CAM device that allows defective rows in one CAM block to be functionally replaced by spare rows from any CAM block in the device. In some embodiments, the CAM device includes a main address decoder, a plurality of CAM blocks, a corresponding plurality of spare address decoders, and a block select circuit. In one embodiment, each CAM block includes a main CAM array having a plurality of rows of CAM cells each coupled to a corresponding word line, and a spare row of CAM cells coupled to a spare word line. Each spare row may be used to functionally replace a defective row in the same CAM block or in any other CAM block by programming the address of the defective row into the corresponding spare address decoder.
摘要翻译： CAM设备允许一个CAM块中的有缺陷的行由设备中任何CAM块的备用行功能替换。在一些实施例中，CAM设备包括主地址解码器，多个CAM块，对应的多个备用地址解码器和块选择电路。在一个实施例中，每个CAM块包括具有多个CAM单元的行的主CAM阵列，每个CAM单元耦合到对应的字线，以及耦合到备用字线的一组备用的CAM单元。每个备用行可以用于通过将缺陷行的地址编程到相应的备用地址解码器中来功能地替换同一CAM块或任何其他CAM块中的有缺陷的行。

8. 发明授权

US06418042B1 Ternary content addressable memory with compare operand selected according to mask value 有权
标题翻译：根据掩码值选择比较操作数的三进制内容可寻址存储器
公开(公告)号：US06418042B1
公开(公告)日：2002-07-09
申请号：US09150517
申请日：1998-09-09
申请人： Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
发明人： Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/00
摘要： A content addressable memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells. The status information may include a match flag, multiple match flag, full flag, skip bit, empty bit, or a device identification for the CAM device. The CAM array may also include ternary CAM cells that are individually maskable so as to effectively store either a logic one, logic zero, or a don't care state for compare operations.
摘要翻译：内容可寻址存储器（CAM）设备。 CAM设备是同步设备，其可以在一个时钟周期内执行所有以下操作：（1）从比较总线接收比较数据; （2）从指令总线接收指令，指示CAM设备将比较数据与CAM阵列中的第一组CAM单元进行比较; （3）比较数据与第一组CAM单元进行比较; （4）生成CAM阵列中存储与比较数据匹配的数据的位置的匹配地址; （5）访问存储在CAM阵列中的CAM单元的第二组中的数据，其中第二组CAM单元可以存储与匹配位置相关联的数据; 和（6）向输出总线输出匹配地址，存储在第二组CAM单元中的数据和/或与匹配地址或第二组CAM单元相对应的状态信息。状态信息可以包括用于CAM设备的匹配标志，多重匹配标志，满标志，跳过位，空位或设备标识。 CAM阵列还可以包括可单独屏蔽的三进制CAM单元，以便有效地存储逻辑1，逻辑0或用于比较操作的无关状态。

9. 发明授权

US06249467B1 Row redundancy in a content addressable memory 有权
标题翻译：内容可寻址内存中的行冗余
公开(公告)号：US06249467B1
公开(公告)日：2001-06-19
申请号：US09590779
申请日：2000-06-08
申请人： Jose Pio Pereira , Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
发明人： Jose Pio Pereira , Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
IPC分类号： G11C700
CPC分类号： G11C15/04 , G11C15/00 , G11C29/785 , G11C29/816
摘要： A CAM device that allows defective rows in one CAM block to be functionally replaced by spare rows from any CAM block in the device. In some embodiments, the CAM device includes a main address decoder, a plurality of CAM blocks, a corresponding plurality of spare address decoders, and a block select circuit. In one embodiment, each CAM block includes a main CAM array having a plurality of rows of CAM cells each coupled to a corresponding word line, and a spare row of CAM cells coupled to a spare word line. Each spare row may be used to functionally replace a defective row in the same CAM block or in any other CAM block by programming the address of the defective row into the corresponding spare address decoder. During subsequent read or write operations, an input address is compared with the programmed addresses stored in the spare address decoders. If there is match, thereby indicating that the selected row is defective and has been replaced, the address decoder storing the matching programmed address enables the spare row in the corresponding CAM block, and the block select circuit enables the corresponding CAM block for the operation, so that the read or write operation accesses the spare row instead of the defective row. If there is not a match, the spare address decoder does not enable the corresponding spare word line, and the block select circuit enables the CAM block identified by the input address for the operation.
摘要翻译： CAM设备允许一个CAM块中的有缺陷的行由设备中任何CAM块的备用行功能替换。在一些实施例中，CAM设备包括主地址解码器，多个CAM块，对应的多个备用地址解码器和块选择电路。在一个实施例中，每个CAM块包括具有多个CAM单元的行的主CAM阵列，每个CAM单元耦合到对应的字线，以及耦合到备用字线的一组备用的CAM单元。每个备用行可以用于通过将缺陷行的地址编程到相应的备用地址解码器中来功能地替换同一CAM块或任何其他CAM块中的有缺陷的行。在随后的读取或写入操作期间，将输入地址与存储在备用地址解码器中的编程地址进行比较。如果存在匹配，从而指示所选行有缺陷并被替换，则存储匹配的编程地址的地址解码器使能相应CAM块中的备用行，并且块选择电路使能相应的CAM块进行操作，使得读取或写入操作访问备用行而不是有缺陷的行。如果不匹配，则备用地址解码器不启用相应的备用字线，并且块选择电路使能由输入地址识别的CAM块用于操作。

10. 发明授权

US6166939A Method and apparatus for selective match line pre-charging in a content addressable memory 失效
标题翻译：用于在内容可寻址存储器中选择性地匹配线路预充电的方法和装置
公开(公告)号：US6166939A
公开(公告)日：2000-12-26
申请号：US351541
申请日：1999-07-12
申请人： Bindiganavale S. Nataraj , Varadarajan Srinivasan , Sandeep Khanna
发明人： Bindiganavale S. Nataraj , Varadarajan Srinivasan , Sandeep Khanna
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04 , G11C15/00
摘要： Match line control circuits are used to selectively charge corresponding match lines in response to the valid bits. If the valid bit is asserted, thereby indicating the valid data is stored in the CAM row, the match line control circuit pre-charges the match line to enable the match line to be responsive to compare operation between a comparand word and data stored in the row. If the valid bit is de-asserted, thereby indicating that any data stored in the row is invalid, the match line control circuit disables the match line by forcing a mismatch condition between the comparand word and data stored in the row. In one embodiment, the match line control circuit includes a pull-up transistor coupled between the match line and a supply voltage and having a gate responsive to the valid bit. In other embodiments, the match line control circuit further includes a pull-down transistor coupled between the match line and a supply voltage and having a gate responsive to a complement of the valid bit.
摘要翻译：匹配线控制电路用于响应于有效位选择性地对相应的匹配线进行充电。如果有效位被断言，则由此指示有效数据被存储在CAM行中，匹配线路控制电路对该匹配线进行预充电以使匹配线能够响应于比较字与存储在行。如果有效位被取消置位，从而指示存储在该行中的任何数据无效，则匹配线控制电路通过强制比较字与存储在该行中的数据之间的失配条件来禁用匹配线。在一个实施例中，匹配线控制电路包括耦合在匹配线和电源电压之间的上拉晶体管，并具有响应于有效位的栅极。在其他实施例中，匹配线控制电路还包括耦合在匹配线和电源电压之间并具有响应于有效位的补码的门的下拉晶体管。

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