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1. 发明授权

US5238868A Bandgap tuning of semiconductor quantum well structures 失效
标题翻译：半导体量子阱结构的带隙调谐
公开(公告)号：US5238868A
公开(公告)日：1993-08-24
申请号：US724437
申请日：1991-07-01
申请人： Boris S. Elman , Emil S. Koteles , Paul Melman , Craig A. Armiento
发明人： Boris S. Elman , Emil S. Koteles , Paul Melman , Craig A. Armiento
IPC分类号： H01L21/18 , H01L21/324 , H01S5/20 , H01S5/34 , H01S5/343
CPC分类号： B82Y20/00 , H01L21/182 , H01L21/3245 , H01S5/34 , H01S5/2063 , H01S5/3413 , H01S5/3432
摘要： A method of selectively tuning the bandedge of a semi-conductor heterostructure includes forming a disordered region which is spatially separated from a quantum well active region, and subsequently annealing the heterostructure so that vacancies/defects in the disordered region diffuse into the quantum well region and enhance interdiffusion at the well-barrier heterojunctions. The tuning is spatially selective when the heterostructure is masked so that exposed portions correspond to regions where bandgap tuning is desirable. The heterostructures of interest are III-V material systems, such as AlGaAs/GaAs, where the active region includes structures such as a single quantum well, a multiple quantum well, or a superlattice.
摘要翻译：选择性地调谐半导体异质结构的带边的方法包括形成与量子阱有源区空间分离的无序区域，随后使异质结构退火，使得无序区域中的空位/缺陷扩散到量子阱区域，增强了屏障异质结的相互扩散。当异质结构被掩蔽时，调谐是空间选择的，使得暴露部分对应于期望带隙调谐的区域。感兴趣的异质结构是III-V材料体系，例如AlGaAs / GaAs，其中活性区域包括诸如单量子阱，多量子阱或超晶格的结构。

2. 发明授权

US5053843A Thermally-stable structure for IMSM photodetectors on GaAs substrates 失效
标题翻译： GaAs衬底上IMSM光电探测器的热稳定结构
公开(公告)号：US5053843A
公开(公告)日：1991-10-01
申请号：US626159
申请日：1990-12-12
申请人： A. N. M. Masum Choudhury , Chirravuri Jagannath , Boris S. Elman , Craig A. Armiento
发明人： A. N. M. Masum Choudhury , Chirravuri Jagannath , Boris S. Elman , Craig A. Armiento
IPC分类号： H01L31/0304 , H01L31/0352 , H01L31/108
CPC分类号： B82Y20/00 , H01L31/03046 , H01L31/035236 , H01L31/1085 , Y02E10/544
摘要： An IMSM photodetector structure comprises a GaAs substrate, a buffer region grown on the substrate, an optically active absorbing layer of In.sub.0.42 Ga.sub.0.58 As grown on the absorbing layer. The buffer region includes in sequence a first layer of In.sub.0.23 Ga.sub.0.77 As, an In.sub.0.46 Ga.sub.0.54 As/GaAs superlattice, and a second layer of In.sub.0.23 Ga.sub.0.77 As. An interdigitated pattern of Schottky metal contacts is fabricated on the Al.sub.0.3 Ga.sub.0.7 As/GaAs superlattice. This structure is useful in fabricating long-wavelength, monolithic receivers based on GaAs MESFET technology since the optical and electrical characteristics of the structure are preserved during the thermal annealing cycle necesary in ion-implaned GaAs MESFET processes.
摘要翻译： IMSM光电检测器结构包括GaAs衬底，在衬底上生长的缓冲区，在吸收层上生长的In 0.42 Ga 0.58 As的光学活性吸收层。缓冲区依次包括In0.23Ga0.77As的第一层，In0.46Ga0.54As / GaAs超晶格和第二层In0.23Ga0.77As。在Al0.3Ga0.7As / GaAs超晶格上制造了肖特基金属触点的交叉图案。该结构在制造基于GaAs MESFET技术的长波长单片接收机中是有用的，因为在离子掺杂的GaAs MESFET工艺中，在热退火循环期间，保留了结构的光学和电学特性。

3. 发明授权

US5182782A Waferboard structure and method of fabricating 失效
标题翻译：晶圆板结构及其制造方法
公开(公告)号：US5182782A
公开(公告)日：1993-01-26
申请号：US817570
申请日：1992-01-07
申请人： Marvin Tabasky , Victor Cataldo , Thomas W. Fitzgerald , Jagannath Chirravuri , Craig A. Armiento , Paul O. Haugsjaa
发明人： Marvin Tabasky , Victor Cataldo , Thomas W. Fitzgerald , Jagannath Chirravuri , Craig A. Armiento , Paul O. Haugsjaa
IPC分类号： G02B6/42 , H01S5/02 , H01S5/40
CPC分类号： H01S5/02 , G02B6/423 , G02B6/4249 , H01S5/4025 , G02B6/4238
摘要： A waferboard assembly incorporates mechanical registration features into a substrate platform to facilitate the passive alignment of lasers integrated on a chip to fibers in integral contact with the substrate. The waferboard includes two front pedestal structures and one side pedestal structure, and two vertical post structures within a mounting region defined by the pedestal structures. The laser chip is mounted on the vertical post structures, and placed in concurrent abutting contact with the pedestal structures. The waferboard is fabricated by etching the substrate to form the front and side pedestal structures, and etching the substrate to define the grooves. In order to form the post structures, a polyimide material is deposited on the substrate using an appropriate mask.
摘要翻译：晶片组件将机械配准特征结合到衬底平台中，以便于集成在芯片上的激光器与衬底完全接触的纤维的被动对准。晶片板包括两个前基座结构和一个侧基座结构，以及在由基座结构限定的安装区域内的两个垂直柱结构。激光芯片安装在垂直柱结构上，并与底座结构同时邻接接触。通过蚀刻基板以形成前侧和底侧基座结构并蚀刻基板以限定凹槽来制造晶片板。为了形成柱结构，使用适当的掩模在基板上沉积聚酰亚胺材料。

4. 发明授权

US4729967A Method of fabricating a junction field effect transistor 失效
标题翻译：制造结型场效应晶体管的方法
公开(公告)号：US4729967A
公开(公告)日：1988-03-08
申请号：US36411
申请日：1987-04-09
申请人： Craig A. Armiento
发明人： Craig A. Armiento
IPC分类号： H01L29/80 , H01L21/28 , H01L21/337 , H01L29/772 , H01L29/808 , H01L21/265
CPC分类号： H01L29/66924 , H01L29/7722 , H01L29/8083 , Y10S148/088 , Y10S438/944
摘要： Method of fabricating a junction field effect transistor, specifically a static induction transistor, which may be of GaAs. Elongated N-type source regions are formed in an N-type epitaxial layer of semiconductor material grown on a substrate. A tri-level mask is formed having elongated openings exposing portions of the epitaxial layer intermediate between the source regions. The openings are wider at the bottom than at the top. P-type gate regions are formed by ion-implanting P-type doping material through the mask openings. Silicon dioxide is deposited through the openings by angle evaporation to form generally trapezoidal-shaped temporary gate members over the gate regions. The tri-level mask is removed, a layer of silicon nitride is deposited, and a layer of masking material is deposited. Some of the masking material is removed; then the temporary gate members and silicon nitride immediately adjacent thereto are removed. Metal for making ohmic contact to the P-type gate regions is deposited through the resulting openings. The remaining masking material is removed, openings are formed in the silicon nitride over the N-type source regions, and metal for making ohmic contact to the N-type source regions is deposited in the openings.

5. 发明授权

US4603469A Fabrication of complementary modulation-doped filed effect transistors 失效
标题翻译：互补调制掺杂场效应晶体管的制造
公开(公告)号：US4603469A
公开(公告)日：1986-08-05
申请号：US715698
申请日：1985-03-25
申请人： Craig A. Armiento , Peter E. Norris
发明人： Craig A. Armiento , Peter E. Norris
IPC分类号： H01L21/8252 , H01L21/20 , H01L21/265
CPC分类号： H01L21/8252
摘要： Method of fabricating a monolithic integrated circuit structure incorporating a complementary pair of GaAs/AlGaAs modulation-doped field effect transistors (MODFET's) including providing a substrate of semi-insulating GaAs, depositing an epitaxial layer of undoped AlGaAs on its surface, and ion-implanting a heavily doped N-type donor region and a heavily doped P-type acceptor region in the undoped AlGaAs. A thin spacer layer of undoped AlGaAs is epitaxially deposited on the previously deposited AlGaAs layer, and an epitaxial layer of undoped GaAs is deposited on the spacer layer. First and second gate members which form Schottky barriers with the GaAs are placed on the GaAs layer overlying portions of the N-type donor region and P-type acceptor region, respectively. N-type source and drain zones are formed in the GaAs layer on opposite sides of the first gate member, and P-type source and drain zones are formed in the GaAs layer on opposite sides of the second gate member. A first MODFET is provided by the N-type donor region, the N-type source and drain, the region of undoped GaAs between the source and drain which form a two-dimensional electron gas region, and the first gate member. A second MODFET complementary to the first is provided by the P-type acceptor region, the P-type source and drain, the region of undoped GaAs between the source and drain which form a two-dimensional hole gas region, and the second gate member.
摘要翻译：制造包含互补对的GaAs / AlGaAs调制掺杂场效应晶体管（MODFET）的单片集成电路结构的方法，包括提供半绝缘GaAs的衬底，在其表面上沉积未掺杂的AlGaAs的外延层，以及离子注入重掺杂的N型施主区域和未掺杂的AlGaAs中的重掺杂的P型受主区域。在先前沉积的AlGaAs层上外延沉积未掺杂的AlGaAs的薄间隔层，并且在间隔层上沉积未掺杂的GaAs的外延层。分别在GaAs层上叠置形成肖特基势垒的第一和第二栅极元件，分别覆盖N型施主区域和P型受主区域的部分。在第一栅极部件的相对侧上的GaAs层中形成有N型源极和漏极区域，并且在第二栅极部件的相对侧的GaAs层中形成P型源极和漏极区域。第一MODFET由N型施主区域，N型源极和漏极，源极和漏极之间的未掺杂GaAs的区域形成二维电子气区域和第一栅极部件提供。与第一个互补的第二个MODFET由P型受主区域，P型源极和漏极，源极和漏极之间的未掺杂GaAs的区域形成二维空穴气体区域，第二栅极部件。

6. 发明授权

US5163108A Method and device for passive alignment of diode lasers and optical fibers 失效
标题翻译：用于二极管激光器和光纤的无源对准的方法和装置
公开(公告)号：US5163108A
公开(公告)日：1992-11-10
申请号：US739587
申请日：1991-08-02
申请人： Craig A. Armiento , Chirravuri Jagannath , Marvin J. Tabasky , Thomas W. Fitzgerald , Harry F. Lockwood , Paul O. Haugsjaa , Mark A. Rothman , Vincent J. Barry , Margaret B. Stern
发明人： Craig A. Armiento , Chirravuri Jagannath , Marvin J. Tabasky , Thomas W. Fitzgerald , Harry F. Lockwood , Paul O. Haugsjaa , Mark A. Rothman , Vincent J. Barry , Margaret B. Stern
IPC分类号： G02B6/42 , H01S5/02 , H01S5/40
CPC分类号： G02B6/423 , G02B6/4249 , H01S5/02 , H01S5/4025 , G02B6/4238
摘要： A method of passively aligning optical receiving elements such as fibers to the active elements of a light generating chip includes the steps of forming two front and one side pedestal structures on the surface of a substrate body, defining a vertical sidewall of the chip to form a mating channel having an edge at a predetermined distance from the first active element, mounting the chip epi-side down on the substrate surface, and positioned the fibers in fiber-receiving channels so that a center line of each fiber is aligned to a center line of a respective active element. When mounted, the front face of the chip is abutting the contact surfaces of the two front pedestals, and the defined sidewall of the mating channel is abutting the contact surface of the side pedestal. The passive alignment procedure is also effective in aligning a single fiber to a single active element.
摘要翻译：将诸如光纤的光接收元件被动地对准发光芯片的有源元件的方法包括以下步骤：在衬底主体的表面上形成两个前和底侧基座结构，限定芯片的垂直侧壁以形成配合通道具有距离第一有源元件预定距离的边缘，将芯片外延安装在基板表面上，并将光纤定位在光纤接收通道中，使得每个光纤的中心线与中心线对准的相应活性元素。当安装时，芯片的前表面抵靠两个前基座的接触表面，并且配合通道的限定侧壁邻接侧基座的接触表面。被动对准程序在将单个光纤对准单个有源元件方面也是有效的。

7. 发明授权

US5077878A Method and device for passive alignment of diode lasers and optical fibers 失效
标题翻译：用于二极管激光和光纤的被动对准的方法和装置
公开(公告)号：US5077878A
公开(公告)日：1992-01-07
申请号：US551219
申请日：1990-07-11
申请人： Craig A. Armiento , Chirravuri Jagannath , Marvin J. Tabasky , Thomas W. Fitzgerald , Harry F. Lockwood , Paul O. Haugsjaa , Mark A. Rothman , Vincent J. Barry , Margaret B. Stern
发明人： Craig A. Armiento , Chirravuri Jagannath , Marvin J. Tabasky , Thomas W. Fitzgerald , Harry F. Lockwood , Paul O. Haugsjaa , Mark A. Rothman , Vincent J. Barry , Margaret B. Stern
IPC分类号： H01S5/00 , G02B6/42 , H01S5/02 , H01S5/026 , H01S5/40
CPC分类号： H01S5/4025 , G02B6/423 , G02B6/4249 , H01S5/02 , G02B6/4238 , Y10S148/095 , Y10T29/413
摘要： A method of passively aligning optical receiving elements such as fibers to the active elements of a light generating chip includes the steps of forming two front and one side pedestal structures on the surface of a substrate body, defining a vertical sidewall of the chip to form a mating channel having an edge at a predetermined distance from the first active element, mounting the chip epi-side down on the substrate surface, and positioning the fibers in fiber-receiving channels to that a center line of each fiber is aligned to a center line of a respective active element. When mounted, the front face of the chip is abutting the contact surfaces of the two front pedestals, and the defined sidewall of the mating channel is abutting the contact surface of the side pedestal. The passive alignment procedure is also effective in aligning a single fiber to a single active element.

8. 发明授权

US06768777B1 Method and apparatus for calculating the number of very high speed digital subscriber line nodes 有权
标题翻译：用于计算非常高速数字用户线路节点数量的方法和装置
公开(公告)号：US06768777B1
公开(公告)日：2004-07-27
申请号：US09604230
申请日：2000-06-27
申请人： Michael Cooperman , Albert M. Forcucci , John W. Lovell , Craig A. Armiento
发明人： Michael Cooperman , Albert M. Forcucci , John W. Lovell , Craig A. Armiento
IPC分类号： H04B300
CPC分类号： H04B3/46
摘要： A method is provided for estimating a number of digital subscriber line nodes (220, 230) required to supply, from a line supply source (200), a geographically distributed network of substantially sequentially numbered twisted pair lines with digital subscriber line service. The method comprises the steps of: storing, in number order, data entries for every twisted pair line of the network, each data entry comprising a pair number and a line length of the respective twisted pair line in relation to the line supply source (200); sorting the entries stored in the database by line length; isolating those sorted entries whose twisted pair lines have a line length greater than a predetermined maximum line length in relation to the line supply source (200); sorting the isolated entries by number; and discriminating, from the sorted isolated entries, the presence of discrete groupings of substantially contiguous entries.
摘要翻译：提供了一种用于估计从线路供应源（200）提供具有数字用户线服务的基本上顺序编号的双绞线的地理分布式网络所需的数字用户线节点（220,230）的数量的方法。该方法包括以下步骤：以数字顺序存储网络的每个双绞线的数据条目，每个数据条目包括相对于线路供应源（200）的各个双绞线的对号码和线路长度）; 按照线路长度对数据库中存储的条目进行排序; 隔离相对于线路供应源（200）的双绞线具有大于预定最大线路长度的线路长度的排序条目; 按数字排序隔离的条目; 并且从排序的隔离条目中区分基本上连续条目的离散分组的存在。

9. 发明授权

US5355386A Monolithically integrated semiconductor structure and method of fabricating such structure 失效
标题翻译：单片半导体结构及其制造方法
公开(公告)号：US5355386A
公开(公告)日：1994-10-11
申请号：US977596
申请日：1992-11-17
申请人： Mark A. Rothman , Chan-Long Shieh , Craig A. Armiento , John A. Thompson , Alfred J. Negri
发明人： Mark A. Rothman , Chan-Long Shieh , Craig A. Armiento , John A. Thompson , Alfred J. Negri
IPC分类号： G02B6/30 , G02B6/36 , G02B6/42 , H01S5/00 , H01S5/02 , H01S5/026 , H01S5/40 , H01S3/25
CPC分类号： G02B6/4249 , G02B6/42 , H01S5/0264 , G02B6/30 , H01S5/0203 , H01S5/026 , H01S5/4025
摘要： A heterostructure device includes a ridge-waveguide laser monolithically integrated with a ridge-waveguide rear facet monitor (RFM). An integral V-groove etched directly into the device substrate enables passive alignment of an optical fiber to the active region of the laser. The laser and RFM facets were formed using an in-situ multistep reactive ion etch process.
摘要翻译：异质结构器件包括与脊 - 波导后小面监视器（RFM）单片集成的脊 - 波导激光器。直接蚀刻到器件衬底中的整体V型沟槽使得光纤能够被激活地对准激光器的有源区域。使用原位多步反应离子蚀刻工艺形成激光器和RFM刻面。

10. 发明授权

US5268066A Method of fabricating waferboard structure 失效
标题翻译：刨花板结构的制作方法
公开(公告)号：US5268066A
公开(公告)日：1993-12-07
申请号：US999513
申请日：1992-12-30
申请人： Marvin Tabasky , Victor Cataldo , Thomas W. Fitzgerald , Jagannath Chirravuri , Craig A. Armiento , Paul O. Haugsjaa
发明人： Marvin Tabasky , Victor Cataldo , Thomas W. Fitzgerald , Jagannath Chirravuri , Craig A. Armiento , Paul O. Haugsjaa
IPC分类号： G02B6/42 , H01S5/02 , H01S5/40 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01S5/4025 , G02B6/423 , G02B6/4249 , H01S5/02 , G02B6/4238
摘要： A waferboard assembly incorporates mechanical registration features into a substrate platform to facilitate the passive alignment of lasers integrated on a chip to fibers in integral contact with the substrate. The waferboard includes two front pedestal structures and one side pedestal structure, and two vertical post structures within a mounting region defined by the pedestal structures. The laser chip is mounted on the vertical post structures, and placed in concurrent abutting contact with the pedestal structures. The waferboard is fabricated by etching the substrate to form the front and side pedestal structures, and etching the substrate to define the grooves. In order to form the post structures, a polyimide material is deposited on the substrate using an appropriate mask.
摘要翻译：晶片组件将机械配准特征结合到衬底平台中，以便于集成在芯片上的激光器与衬底完全接触的纤维的被动对准。晶片板包括两个前基座结构和一个侧基座结构，以及在由基座结构限定的安装区域内的两个垂直柱结构。激光芯片安装在垂直柱结构上，并与底座结构同时邻接接触。通过蚀刻基板以形成前侧和底侧基座结构并蚀刻基板以限定凹槽来制造晶片板。为了形成柱结构，使用适当的掩模在基板上沉积聚酰亚胺材料。

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