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1. 发明授权

US07354847B2 Method of trimming technology 有权
标题翻译：修边技术方法
公开(公告)号：US07354847B2
公开(公告)日：2008-04-08
申请号：US10764913
申请日：2004-01-26
申请人： Bor-Wen Chan , Yi-Chun Huang , Baw-Ching Perng , Hun-Jan Tao
发明人： Bor-Wen Chan , Yi-Chun Huang , Baw-Ching Perng , Hun-Jan Tao
IPC分类号： H01L21/3205 , H01L27/10
CPC分类号： H01L21/28123 , H01L21/0271 , H01L21/0338 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L21/823437
摘要： A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr/O2/Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1−w2) is possible than in prior art methods.
摘要翻译：描述了在MOSFET的栅电极制造期间修整光致抗蚀剂层的工艺。在较厚的有机底层上具有顶部光致抗蚀剂层的双层叠层以193nm或157nm辐射图案曝光以形成顶层中具有宽度w 1 1的特征。通过底层的图案转移通过基于H 2 N 2 N 2 N 2 SO 3和SO 2 H 2化学的各向异性蚀刻进行。通过HBr / O 2 / Cl 2等离子体将形成在双层叠层中的特征修剪10nm以上至宽度w 2 2 <！ - SIPO

2. 发明授权

US06812044B2 Advanced control for plasma process 有权
标题翻译：等离子体工艺的先进控制
公开(公告)号：US06812044B2
公开(公告)日：2004-11-02
申请号：US10324465
申请日：2002-12-19
申请人： Hsien-Kuang Chiu , Bor-Wen Chan , Baw-Ching Perng , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Hsien-Kuang Chiu , Bor-Wen Chan , Baw-Ching Perng , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L2100
CPC分类号： H01J37/32935 , H01L21/67069 , H01L21/67253
摘要： A method for monitoring plasma parameters during a plasma process such as a plasma etching process, comparing the measured plasma parameters to predetermined parameter specifications, and either terminating the plasma process or modifying the plasma process in progress to re-establish the plasma parameters within the parameter specifications. The plasma parameters may be measured by the self-excited electron resonance spectroscopy (SEEKS) technique or by microwave interferometry.
摘要翻译：一种用于在诸如等离子体蚀刻工艺的等离子体工艺期间监测等离子体参数的方法，将测量的等离子体参数与预定参数规格进行比较，以及终止等离子体处理或修改正在进行的等离子体处理，以重新建立参数内的等离子体参数规格。等离子体参数可以通过自激电子共振光谱（SEEKS）技术或通过微波干涉测量来测量。

3. 发明授权

US07122484B2 Process for removing organic materials during formation of a metal interconnect 有权
标题翻译：在形成金属互连件期间去除有机材料的方法
公开(公告)号：US07122484B2
公开(公告)日：2006-10-17
申请号：US10833558
申请日：2004-04-28
申请人： Baw-Ching Perng , Yi-Chen Huang , Jun-Lung Huang , Bor-Wen Chan , Peng-Fu Hsu , Hsin-Ching Shih , Lawrance Hsu , Hun-Jan Tao
发明人： Baw-Ching Perng , Yi-Chen Huang , Jun-Lung Huang , Bor-Wen Chan , Peng-Fu Hsu , Hsin-Ching Shih , Lawrance Hsu , Hun-Jan Tao
IPC分类号： H01L21/469 , H01L21/44
CPC分类号： H01L21/76814 , C11D3/3947 , C11D7/50 , C11D11/0047 , G03F7/423 , H01L21/02063 , H01L21/02101 , H01L21/31133 , H01L21/31144 , H01L21/76808
摘要： A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.
摘要翻译：公开了一种从基底上的低k电介质层和金属层上方的开口除去有机材料的方法。将由一种或多种添加剂如羟胺或铵盐组成的臭氧水溶液作为喷雾或浸渍施用。可以加入螯合剂以保护金属层免于氧化。可以将二酮加入到臭氧水溶液中或在随后的步骤中以气相或液相的形式施加，以除去在臭氧处理期间形成的任何金属氧化物。可以使用包括CO 2和臭氧的超临界流体混合物来除去不易被上述液体溶液剥离的有机残留物。去除方法防止低k电介质层的介电常数和折射率的变化，并且清洁地去除提高器件性能的残留物。

4. 发明申请

US20050245082A1 Process for removing organic materials during formation of a metal interconnect 有权
标题翻译：在形成金属互连件期间去除有机材料的方法
公开(公告)号：US20050245082A1
公开(公告)日：2005-11-03
申请号：US10833558
申请日：2004-04-28
申请人： Baw-Ching Perng , Yi-Chen Huang , Jun-Lung Huang , Bor-Wen Chan , Peng-Fu Hsu , Hsin-Ching Shih , Lawrance Sheu , Hun-Jan Tao
发明人： Baw-Ching Perng , Yi-Chen Huang , Jun-Lung Huang , Bor-Wen Chan , Peng-Fu Hsu , Hsin-Ching Shih , Lawrance Sheu , Hun-Jan Tao
IPC分类号： C11D7/50 , C11D11/00 , G03F7/42 , H01L21/02 , H01L21/311 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76814 , C11D3/3947 , C11D7/50 , C11D11/0047 , G03F7/423 , H01L21/02063 , H01L21/02101 , H01L21/31133 , H01L21/31144 , H01L21/76808
摘要： A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.
摘要翻译：公开了一种从基底上的低k电介质层和金属层上方的开口除去有机材料的方法。将由一种或多种添加剂如羟胺或铵盐组成的臭氧水溶液作为喷雾或浸渍施用。可以加入螯合剂以保护金属层免于氧化。可以将二酮加入到臭氧水溶液中或在随后的步骤中以气相或液相的形式施加，以除去在臭氧处理期间形成的任何金属氧化物。可以使用包括CO 2和臭氧的超临界流体混合物来除去不易被上述液体溶液剥离的有机残留物。去除方法防止低k电介质层的介电常数和折射率的变化，并且清洁地去除提高器件性能的残留物。

5. 发明申请

US20060009001A1 A Recessed Polysilicon Gate Structure for a Strained Silicon MOSFET Device 有权
标题翻译：用于应变硅MOSFET器件的嵌入式多晶硅栅极结构
公开(公告)号：US20060009001A1
公开(公告)日：2006-01-12
申请号：US10864952
申请日：2004-06-10
申请人： Yi-Chun Huang , Bor-Wen Chan , Baw-Ching Perng , Lawrence Sheu , Huan-Jan Tao , Chih-Hsin Ko , Chun-Chieh Lin
发明人： Yi-Chun Huang , Bor-Wen Chan , Baw-Ching Perng , Lawrence Sheu , Huan-Jan Tao , Chih-Hsin Ko , Chun-Chieh Lin
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/76
CPC分类号： H01L29/66545 , H01L21/823807 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7845 , H01L29/7848
摘要： Abstract of the Disclosure A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portion reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.
摘要翻译：发明内容已经开发出通过使用相邻和周围的硅 - 锗形状在应变硅层中形成用于MOSFET器件的沟道区的方法。该方法同时形成导电栅极结构的顶部中的凹部并且在半导体衬底的不被栅极结构占据的部分中，或者位于导电栅极结构的侧面上的虚设间隔物。选择性限定的凹槽将用于随后容纳硅锗形状，其中硅 - 锗形状位于半导体衬底的凹陷中，从而诱导期望的应变通道区域。导电栅极结构和半导体衬底部分的凹陷减少了在合金层的外延生长期间跨越侧壁间隔物表面的硅 - 锗桥接的风险，从而降低了栅极到衬底泄漏或短路的风险。

6. 发明申请

US20050164478A1 Novel method of trimming technology 有权
标题翻译：新型修边技术
公开(公告)号：US20050164478A1
公开(公告)日：2005-07-28
申请号：US10764913
申请日：2004-01-26
申请人： Bor-Wen Chan , Yi-Chun Huang , Baw-Ching Perng , Hun-Jan Taq
发明人： Bor-Wen Chan , Yi-Chun Huang , Baw-Ching Perng , Hun-Jan Taq
IPC分类号： H01L21/027 , H01L21/033 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/4763 , H01L21/8234
CPC分类号： H01L21/28123 , H01L21/0271 , H01L21/0338 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L21/823437
摘要： A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr/O2/Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1−w2) is possible than in prior art methods.
摘要翻译：描述了在MOSFET的栅电极制造期间修整光致抗蚀剂层的工艺。在较厚的有机底层上具有顶部光致抗蚀剂层的双层叠层以193nm或157nm辐射图案曝光以形成顶层中具有宽度w 1 1的特征。通过底层的图案转移通过基于H 2 N 2 N 2 N 2 SO 3和SO 2 H 2化学的各向异性蚀刻进行。通过HBr / O 2 / Cl 2等离子体将形成在双层叠层中的特征修剪10nm以上至宽度w 2 2 <！ - SIPO

7. 发明授权

US07172933B2 Recessed polysilicon gate structure for a strained silicon MOSFET device 有权
标题翻译：用于应变硅MOSFET器件的嵌入式多晶硅栅极结构
公开(公告)号：US07172933B2
公开(公告)日：2007-02-06
申请号：US10864952
申请日：2004-06-10
申请人： Yi-Chun Huang , Bow-Wen Chan , Baw-Ching Perng , Lawrence Sheu , Hun-Jan Tao , Chih-Hsin Ko , Chun-Chieh Lin
发明人： Yi-Chun Huang , Bow-Wen Chan , Baw-Ching Perng , Lawrence Sheu , Hun-Jan Tao , Chih-Hsin Ko , Chun-Chieh Lin
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/20 , H01L21/205 , H01L21/425 , H01L21/265 , H01L21/44 , H01L21/28 , H01L21/4763 , H01L21/3205
CPC分类号： H01L29/66545 , H01L21/823807 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7845 , H01L29/7848
摘要： A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.
摘要翻译：已经开发了通过使用相邻和周围的硅 - 锗形状在应变硅层中形成用于MOSFET器件的沟道区域的方法。该方法同时形成导电栅极结构的顶部中的凹部并且在半导体衬底的不被栅极结构占据的部分中，或者位于导电栅极结构的侧面上的虚设间隔物。选择性限定的凹槽将用于随后容纳硅锗形状，其中硅 - 锗形状位于半导体衬底的凹陷中，从而诱导期望的应变通道区域。导电栅极结构和半导体衬底部分的凹陷减少了在合金层的外延生长期间跨越侧壁间隔物的硅 - 锗桥接的风险，从而降低了栅极到衬底泄漏或短路的风险。

8. 发明申请

US20050181590A1 Process for patterning high-k dielectric material 有权
标题翻译：图案化高k电介质材料的工艺
公开(公告)号：US20050181590A1
公开(公告)日：2005-08-18
申请号：US11101774
申请日：2005-04-08
申请人： Hsien-Kuang Chiu , Baw-Ching Perng , Hun-Jan Tao
发明人： Hsien-Kuang Chiu , Baw-Ching Perng , Hun-Jan Tao
IPC分类号： C23F1/00 , H01L21/20 , H01L21/28 , H01L21/306 , H01L21/311 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L29/78
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method further includes a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.
摘要翻译：提供了一种图案化高k介电材料层的方法，其可用于制造半导体器件。在高k电介质层上进行第一蚀刻。在第一蚀刻之后，用第一蚀刻蚀刻的高k电介质层的一部分保留。执行高k电介质层的第二蚀刻以去除高k电介质层的剩余部分。第二蚀刻不同于第一蚀刻。优选地，第一蚀刻是干蚀刻工艺，第二蚀刻是湿蚀刻工艺。该方法还包括在第一次蚀刻之后和第二次蚀刻之前等离子体灰化高k电介质层的剩余部分的工艺。

9. 发明授权

US06498067B1 Integrated approach for controlling top dielectric loss during spacer etching 有权
标题翻译：在间隔蚀刻期间控制顶部介电损耗的集成方法
公开(公告)号：US06498067B1
公开(公告)日：2002-12-24
申请号：US10139021
申请日：2002-05-02
申请人： Baw-Ching Perng , Ming-Huang Tsai , Ju-Wang Hsu , Hun-Jan Tao
发明人： Baw-Ching Perng , Ming-Huang Tsai , Ju-Wang Hsu , Hun-Jan Tao
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L29/6656
摘要： A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions of sides of a gate structure in which an initial insulator spacer had been removed during an over etch cycle used for definition of the initial insulator spacer. The re-establishment of insulator spacer shapes provides a composite insulator spacer offering reduced risk of gate to substrate leakage or shorts, that can occur during a subsequent salicide procedure from the presence of metal silicide stringers or ribbons formed on, and residing on the composite insulator spacer.
摘要翻译：已经开发了在MOSFET栅极结构的侧面上形成复合绝缘体间隔物的工艺。该工艺特征是在栅极结构的侧面的顶部部分上形成额外的绝缘体间隔物形状，其中在用于限定初始绝缘体间隔物的过蚀刻循环期间已经去除了初始绝缘体间隔物。重新建立绝缘体间隔物形状提供了一种复合绝缘体间隔物，其降低了栅极与衬底泄漏或短路的风险，这可能在随后的自对准硅化物过程中发生，从存在金属硅化物桁条或形成在复合绝缘体上的带状物间隔

10. 发明授权

US07148114B2 Process for patterning high-k dielectric material 有权
标题翻译：图案化高k电介质材料的工艺
公开(公告)号：US07148114B2
公开(公告)日：2006-12-12
申请号：US11101774
申请日：2005-04-08
申请人： Hsien-Kuang Chiu , Baw-Ching Perng , Hun-Jan Tao
发明人： Hsien-Kuang Chiu , Baw-Ching Perng , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method further includes a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.
摘要翻译：提供了一种图案化高k介电材料层的方法，其可用于制造半导体器件。在高k电介质层上进行第一蚀刻。在第一蚀刻之后，用第一蚀刻蚀刻的高k电介质层的一部分保留。执行高k电介质层的第二蚀刻以去除高k电介质层的剩余部分。第二蚀刻不同于第一蚀刻。优选地，第一蚀刻是干蚀刻工艺，第二蚀刻是湿蚀刻工艺。该方法还包括在第一次蚀刻之后和第二次蚀刻之前等离子体灰化高k电介质层的剩余部分的工艺。

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