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1. 发明授权

US4092730A Data processor with read-only-memory processor and partial solution push-down stack 失效
标题翻译：具有只读存储器处理器和部分解决方案的数据处理器
公开(公告)号：US4092730A
公开(公告)日：1978-05-30
申请号：US781605
申请日：1977-03-28
申请人： Bobby G. Burkett , Raymond W. Henry
发明人： Bobby G. Burkett , Raymond W. Henry
IPC分类号： G05B19/05 , G06F13/00 , G06F9/00 , G06F15/20
CPC分类号： G05B19/05 , G05B2219/1188 , G05B2219/15054
摘要： A data processor such as a programmable logic controller utilizes a read-only-memory boolean logic processor for generating solutions to complex boolean equations. The read-only-memory processor includes a plurality of address inputs for selectively addressing memory locations thereof in accordance with applied boolean data and multi-bit instructions. The contents of the addressed memory location represents the solution or partial solution to a boolean equation. A memory, in the form of a push-down stack reversible serial storage means, is coupled to the output of the processor for receiving and storing the single-bit partial solutions, and is coupled to an address input of the processor for transferring partial solutions stored therein to the processor means for further processing. The partial solutions are stored in the reversible storage means in a predetermined order and are transferred from the reversible storage means to the address input of the processor means for further processing in the reverse of said predetermined order.

2. 发明授权

US4215396A Intelligent programmable process control system 失效
标题翻译：智能可编程序控制系统
公开(公告)号：US4215396A
公开(公告)日：1980-07-29
申请号：US936538
申请日：1978-08-24
申请人： Raymond W. Henry , Bobby G. Burkett , Michael L. Bunyard
发明人： Raymond W. Henry , Bobby G. Burkett , Michael L. Bunyard
IPC分类号： G05B19/05 , G06F15/16 , G06F15/46
CPC分类号： G05B19/052 , G05B2219/1105 , G05B2219/1159 , G05B2219/1161 , G05B2219/1188 , G05B2219/15018 , G05B2219/15048 , G05B2219/15127
摘要： An intelligent programmable process control system for controlling industrial processing and manufacturing equipment and the like utilizes a unique system of cooperating multiple processors. A digital processor is utilized for controlling the analog portion of the processing equipment, and a boolean processor is utilized for sequencing and controlling the on/off states of controllable devices. Along the process communication means is provided for communications between the processors. In one embodiment, a circuit is provided for accomplishing parallel digital I/O, accessible by the digital processor for additional control of the analog processing equipment.
摘要翻译：用于控制工业加工和制造设备等的智能可编程序过程控制系统利用协作的多处理器的独特系统。数字处理器用于控制处理设备的模拟部分，并且使用布尔处理器来排序和控制可控设备的开/关状态。沿着处理通信装置提供处理器之间的通信。在一个实施例中，提供了用于实现并行数字I / O的电路，可由数字处理器访问以用于模拟处理设备的附加控制。

3. 发明授权

US3982230A Programmable logic controller with flag storage 失效
标题翻译：具有标志存储的可编程逻辑控制器
公开(公告)号：US3982230A
公开(公告)日：1976-09-21
申请号：US431589
申请日：1974-01-07
申请人： Bobby G. Burkett , Raymond W. Henry
发明人： Bobby G. Burkett , Raymond W. Henry
IPC分类号： G05B19/05 , G06F12/06 , G06F3/06
CPC分类号： G06F12/0684 , G05B19/05 , G05B2219/11101 , G05B2219/1159 , G05B2219/1168 , G05B2219/13004 , G05B2219/13012 , G05B2219/13128 , G05B2219/15018 , G05B2219/15054
摘要： A programmable logic controller has input elements sampled to determine status in each of multicomponent lines of a relay ladder network. Output elements in the network connect power voltage sources to power utilization units and disconnect the same in accordance with a programmed set of instructions stored in a controller memory to satisfy operating conditions required of the ladder network. Sample means sequentially generate a set of one bit words, one word representing the state of each of the input elements. A set of one bit output control states is generated, one state for each output element in dependence upon the states of the input elements. Timing means operable once each half cycle of the power voltage initiates generation and storage in a semiconductor read/write image register of one bit input words and output control states.Further, the timing means includes control means for sequentially instituting a serial I/O mode in which the input elements are sampled and the output states are read out of the register and applied to the output elements followed by a run mode in which a new set of control states is established and stored in the register.
摘要翻译：可编程逻辑控制器具有被采样的输入元件，以确定梯形网络中多条线路中的每个状态。网络中的输出元件将电源电压源连接到功率利用单元，并根据存储在控制器存储器中的编程指令集将其断开，以满足梯形网络所需的操作条件。采样装置顺序地生成一组一个位字，一个字表示每个输入元件的状态。产生一组一位输出控制状态，根据输入元件的状态为每个输出元件提供一个状态。一旦电源电压的每个半周期在一位输入字和输出控制状态的半导体读/写映像寄存器中产生和存储，定时装置就可操作。

4. 发明授权

US4030080A Variable module memory 失效
标题翻译：可变模块存储器
公开(公告)号：US4030080A
公开(公告)日：1977-06-14
申请号：US643970
申请日：1975-12-24
申请人： Bobby G. Burkett , Raymond W. Henry
发明人： Bobby G. Burkett , Raymond W. Henry
IPC分类号： G05B19/05 , G06F12/06 , G06F13/00 , G11C9/00
CPC分类号： G05B19/05 , G06F12/0684 , G05B2219/11101 , G05B2219/1168 , G05B2219/1188 , G05B2219/13004 , G05B2219/13012 , G05B2219/15054
摘要： A variable module memory, particularly suitable for use in a programmable controller, includes a set of up-to-N memory modules each for storing a plurality of words of n bits. N receptacle means are provided for receiving the set of memory modules and for coupling the received memory modules to a common serial bus. Control means is provided, coupled via said receptacle means, to said up-to-N memory modules for providing address signals for selectively addressing the words of a selected memory module to provide the contents stored therein serially to said common serial bus. A pull-up resistor connecting a predetermined voltage to a common serial bus detects the absence of memory modules in the receptacles and forces the serial bus to a predetermined binary state for all bits or all words for a vacant receptacle means.
摘要翻译：特别适用于可编程控制器的可变模块存储器包括一组N个存储器模块，每个存储器模块用于存储n位的多个字。提供N个插座装置用于接收该组存储器模块并将接收到的存储器模块耦合到公共串行总线。提供了经由所述插座装置耦合到所述直到N个存储器模块的控制装置，用于提供用于选择性地寻址选定存储器模块的字的地址信号，以将其中存储的内容串行地提供给所述公共串行总线。将预定电压连接到公共串行总线的上拉电阻检测插座中不存在存储器模块，并迫使串行总线对于所有位或对于空插座装置的所有字来说是预定的二进制状态。

5. 发明授权

US3953834A Programmable logic controller with push down stack 失效
标题翻译：可编程逻辑控制器，带下推叠
公开(公告)号：US3953834A
公开(公告)日：1976-04-27
申请号：US431538
申请日：1974-01-07
申请人： Bobby G. Burkett , Raymond W. Henry
发明人： Bobby G. Burkett , Raymond W. Henry
IPC分类号： G05B19/05 , G06F12/06 , G06F15/20 , G06F9/06 , G06F13/00
CPC分类号： G06F12/0684 , G05B19/05 , G05B2219/11101 , G05B2219/1168 , G05B2219/1188 , G05B2219/13004 , G05B2219/13012 , G05B2219/15054
摘要： A programmable logic controller implemented in semiconductor integrated circuits which contains a memory for storing multi bit instructions and one bit data words with a processor selectively coupled to the memory for operating on the data in accordance with the instruction. A one bit word width push down stack is selectively connected to the processor for storing partial solutions to processor computations. The partial solutions are read from the stack in reverse order to entry thereof in response to completion of calculations of another part of the computations. The solution to the other part is combined with a partial solution retrieved from the push down stack.
摘要翻译：在半导体集成电路中实现的可编程逻辑控制器，其包含用于存储多位指令的存储器和具有选择性地耦合到存储器的处理器的一位数据字，以根据指令对数据进行操作。有选择地将一个字宽的下推堆叠连接到处理器，用于存储处理器计算的部分解决方案。响应于计算的另一部分的计算的完成，从堆栈读取部分解决方案以与其进入相反。对另一部分的解决方案与从推下堆栈检索的部分解决方案组合。

6. 发明授权

US4215395A Dual microprocessor intelligent programmable process control system 失效
标题翻译：双微处理器智能可编程序控制系统
公开(公告)号：US4215395A
公开(公告)日：1980-07-29
申请号：US936533
申请日：1978-08-24
申请人： Michael L. Bunyard , Bobby G. Burkett
发明人： Michael L. Bunyard , Bobby G. Burkett
IPC分类号： G05B19/05 , G06F15/16 , G06F15/46
CPC分类号： G05B19/052 , G05B2219/1117 , G05B2219/1159 , G05B2219/1205 , G05B2219/13001 , G05B2219/15048 , G05B2219/15127
摘要： An intelligent programmable process control system for controlling industrial processing and manufacturing equipment and the like utilizes a unique system of cooperating multiple microprocessors. A multi-bit microprocessor is utilized for controlling the analog portion of the processing equipment, and a single-bit microprocessor is utilized for sequencing. The control processor has overall supervisory control. An arbitration circuit for resolving simultaneous or phased access to memory by the two microprocessors is provided. In addition, a circuit is provided for accomplishing parallel I/O, again accessible by both microprocessors. In one embodiment, means for linking arithmetic functions and non-arithmetic (logic) functions within a boolean-type instruction set is provided.
摘要翻译：用于控制工业加工和制造设备等的智能可编程过程控制系统利用协作的多个微处理器的独特系统。利用多位微处理器来控制处理设备的模拟部分，并利用单位微处理器进行排序。控制处理器具有全面的监控。提供了一种用于解决由两个微处理器同时或分阶段访问存储器的仲裁电路。此外，还提供了一个用于完成并行I / O的电路，可再次由两个微处理器访问。在一个实施例中，提供了用于链接布尔型指令集内的算术函数和非算术（逻辑）函数的装置。

7. 发明授权

US4215398A Dual microprocessor intelligent programmable process control system with communication link 失效
标题翻译：双微处理器智能可编程序控制系统，具有通讯链路
公开(公告)号：US4215398A
公开(公告)日：1980-07-29
申请号：US936422
申请日：1978-08-24
申请人： Bobby G. Burkett , Michael L. Bunyard
发明人： Bobby G. Burkett , Michael L. Bunyard
IPC分类号： G05B19/05 , G06F15/46 , G06F15/16
CPC分类号： G05B19/052 , G05B2219/1159 , G05B2219/1161 , G05B2219/1204 , G05B2219/1205 , G05B2219/15048 , G05B2219/15127
摘要： An intelligent programmable process control system for controlling industrial processing and manufacturing equipment and the like utilizes a unique system of cooperating dual microprocessors. A digital microprocessor is utilized for digital computation and for controlling the analog portion of the processing equipment, and a boolean microprocessor is utilized for sequencing and for controlling the on/off states of devices located along the process in response to the on/off states of sensors located along the process according to a sequence of boolean logic functions. The digital microprocessor has overall supervisory control. Common memory provides a communication link between the two microprocessors. An arbitration circuit for resolving simultaneous or phased access to memory by the two microprocessors is provided. In addition, a circuit is provided for accomplishing parallel digital input/output functions, again accessible by both microprocessors. In one embodiment, means for linking arithmetic functions and non-arithmetic logic functions within a boolean-type instruction set is provided.
摘要翻译：用于控制工业加工和制造设备等的智能可编程序过程控制系统利用协作的双微处理器的独特系统。数字微处理器用于数字计算和用于控制处理设备的模拟部分，并且使用布尔微处理器来对序列进行排序和控制，以响应于开/关状态来控制沿着处理的设备的开/关状态根据布尔逻辑函数序列沿着过程定位传感器。数字微处理器具有全面的监控功能。通用存储器提供两个微处理器之间的通信链路。提供了一种用于解决由两个微处理器同时或分阶段访问存储器的仲裁电路。另外，提供了一种用于实现并行数字输入/输出功能的电路，可再次由两个微处理器访问。在一个实施例中，提供了用于在布尔型指令集内链接算术函数和非算术逻辑函数的装置。

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