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1. 发明申请

US20110109348A1 DYNAMIC COMPARATOR WITH BACKGROUND OFFSET CALIBRATION 有权
标题翻译：具有背景偏移校准的动态比较器
公开(公告)号：US20110109348A1
公开(公告)日：2011-05-12
申请号：US12640016
申请日：2009-12-17
申请人： Bo-Wei Chen , Tim-Kuei Shia , Ji-Eun Jang
发明人： Bo-Wei Chen , Tim-Kuei Shia , Ji-Eun Jang
IPC分类号： H03K5/22
CPC分类号： H03K5/2481
摘要： A dynamic comparator with background offset calibration is provided. The dynamic comparator includes at least one input differential pair, a first back-to-back inverter, a second back-to-back inverter, and an integrator. The input differential pair includes two current branches, wherein one of the current branches has an input referred offset. The first back-to-back inverter determines which one of the two current branches has the input referred offset in response to a first clock signal and generates two control signals accordingly. The integrator generates two calibration voltages for the input differential pair in response to the two control signals, so as to calibrate the input referred offset. The second back-to-back inverter determines a difference between two input signals received by the input differential pair after the input referred offset is calibrated in response to a second clock signal and outputs two comparison signals accordingly.
摘要翻译：提供了具有背景偏移校准的动态比较器。动态比较器包括至少一个输入差分对，第一背对背反相器，第二背对背反相器和积分器。输入差分对包括两个电流分支，其中当前分支中的一个具有输入参考偏移。第一背对背反相器确定两个电流分支中的哪一个响应于第一时钟信号而具有参考的输入偏移，并相应地产生两个控制信号。积分器响应于两个控制信号为输入差分对产生两个校准电压，以校准输入参考偏移。第二背对背逆变器确定在响应于第二时钟信号校准输入参考偏移之后由输入差分对接收的两个输入信号之间的差异，并相应地输出两个比较信号。

2. 发明授权

US08198921B2 Dynamic comparator with background offset calibration 有权
标题翻译：具有背景偏移校准的动态比较器
公开(公告)号：US08198921B2
公开(公告)日：2012-06-12
申请号：US12640016
申请日：2009-12-17
申请人： Bo-Wei Chen , Tim-Kuei Shia , Ji-Eun Jang
发明人： Bo-Wei Chen , Tim-Kuei Shia , Ji-Eun Jang
IPC分类号： H03K5/22
CPC分类号： H03K5/2481
摘要： A dynamic comparator with background offset calibration is provided. The dynamic comparator includes at least one input differential pair, a first back-to-back inverter, a second back-to-back inverter, and an integrator. The input differential pair includes two current branches, wherein one of the current branches has an input referred offset. The first back-to-back inverter determines which one of the two current branches has the input referred offset in response to a first clock signal and generates two control signals accordingly. The integrator generates two calibration voltages for the input differential pair in response to the two control signals, so as to calibrate the input referred offset. The second back-to-back inverter determines a difference between two input signals received by the input differential pair after the input referred offset is calibrated in response to a second clock signal and outputs two comparison signals accordingly.
摘要翻译：提供了具有背景偏移校准的动态比较器。动态比较器包括至少一个输入差分对，第一背对背反相器，第二背对背反相器和积分器。输入差分对包括两个电流分支，其中当前分支中的一个具有输入参考偏移。第一背对背反相器确定两个电流分支中的哪一个响应于第一时钟信号而具有参考的输入偏移，并相应地产生两个控制信号。积分器响应于两个控制信号为输入差分对产生两个校准电压，以校准输入参考偏移。第二背对背逆变器确定在响应于第二时钟信号校准输入参考偏移之后由输入差分对接收的两个输入信号之间的差异，并相应地输出两个比较信号。

3. 发明申请

US20120001175A1 SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING A COUPLING EFFECT OF A TEST-DISABLE TRANSMISSION LINE 有权
标题翻译：能够抑制测试传输线的耦合效应的半导体器件
公开(公告)号：US20120001175A1
公开(公告)日：2012-01-05
申请号：US13229086
申请日：2011-09-09
申请人： Jeong-Yoon AHN , Ji-Eun Jang , Young-Jun Ku
发明人： Jeong-Yoon AHN , Ji-Eun Jang , Young-Jun Ku
IPC分类号： H01L23/58
CPC分类号： G11C29/46 , G11C29/02 , G11C29/025 , G11C29/1201 , G11C2029/1206
摘要： Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.
摘要翻译：半导体器件和半导体存储器件包括多个内部电路，其被配置为响应于它们各自的测试模式信号执行测试操作;以及多个测试模式控制单元，被配置为响应于所述内部电路被禁用而控制内部电路的测试操作一个测试信号。

4. 发明授权

US07929355B2 Memory device performing write leveling operation 失效
标题翻译：执行写平均操作的内存设备
公开(公告)号：US07929355B2
公开(公告)日：2011-04-19
申请号：US11819815
申请日：2007-06-29
申请人： Ji-Eun Jang
发明人： Ji-Eun Jang
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/1039 , G11C7/106 , G11C7/1066 , G11C7/1069
摘要： A memory device includes a multiplexing unit, a pipe latch unit, and an output driver. The multiplexing unit outputs data input from global input/output lines in a normal mode and outputs write leveling data in a writing leveling mode being entered in response to a write leveling signal. The pipe latch unit latches the data outputted from the multiplexing unit and outputting the latched data. The output driver outputs the latched data outputted from the pipe latch unit.
摘要翻译：存储装置包括多路复用单元，管锁存单元和输出驱动器。复用单元以正常模式输出从全局输入/输出线输入的数据，并响应写入调平信号输入写入调平模式的写入均衡数据。管锁存单元锁存从复用单元输出的数据并输出锁存数据。输出驱动器输出从管锁单元输出的锁存数据。

5. 发明授权

US07853842B2 Semiconductor memory device with ZQ calibration 失效
标题翻译：具有ZQ校准的半导体存储器件
公开(公告)号：US07853842B2
公开(公告)日：2010-12-14
申请号：US11967528
申请日：2007-12-31
申请人： Ki-Ho Kim , Ji-Eun Jang
发明人： Ki-Ho Kim , Ji-Eun Jang
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C5/063 , G11C29/028 , G11C29/50008
摘要： A semiconductor memory device is capable of outputting calibration codes to an external circuit. The semiconductor memory device includes a data output control unit for controlling an output of data, a calibration code output control unit for transmitting calibration codes to determine a termination resistance value, a test mode signal generating unit for generating a test mode signal which is enabled in the test mode for outputting the calibration codes, and a test mode control unit for selectively outputting the data or the calibration codes in response to the test mode signal.
摘要翻译：半导体存储器件能够向外部电路输出校准代码。半导体存储器件包括用于控制数据输出的数据输出控制单元，用于发送校准代码以确定终端电阻值的校准代码输出控制单元，用于产生测试模式信号的测试模式信号生成单元，用于输出校准代码的测试模式，以及用于响应于测试模式信号选择性地输出数据或校准代码的测试模式控制单元。

6. 发明申请

US20080304336A1 SEMICONDUCTOR MEMORY DEVICE WITH ZQ CALIBRATION 失效
标题翻译：具有ZQ校准的半导体存储器件
公开(公告)号：US20080304336A1
公开(公告)日：2008-12-11
申请号：US11967528
申请日：2007-12-31
申请人： Ki-Ho KIM , Ji-Eun Jang
发明人： Ki-Ho KIM , Ji-Eun Jang
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C5/063 , G11C29/028 , G11C29/50008
摘要： A semiconductor memory device is capable of outputting calibration codes to an external circuit. The semiconductor memory device includes a data output control unit for controlling an output of data, a calibration code output control unit for transmitting calibration codes to determine a termination resistance value, a test mode signal generating unit for generating a test mode signal which is enabled in the test mode for outputting the calibration codes, and a test mode control unit for selectively outputting the data or the calibration codes in response to the test mode signal.
摘要翻译：半导体存储器件能够向外部电路输出校准代码。半导体存储器件包括用于控制数据输出的数据输出控制单元，用于发送校准代码以确定终端电阻值的校准代码输出控制单元，用于产生测试模式信号的测试模式信号生成单元，用于输出校准代码的测试模式，以及用于响应于测试模式信号选择性地输出数据或校准代码的测试模式控制单元。

7. 发明授权

US07362167B2 Voltage generator 有权
标题翻译：电压发生器
公开(公告)号：US07362167B2
公开(公告)日：2008-04-22
申请号：US11526815
申请日：2006-09-26
申请人： Kee-Teok Park , Ji-Eun Jang
发明人： Kee-Teok Park , Ji-Eun Jang
IPC分类号： G05F1/10
CPC分类号： G11C5/14 , G11C5/148
摘要： A voltage generator reduces a stand by current in a stand by or a self-refresh mode and shortens a response time in an active mode by selectively driving a control transistor of a final driver. A core voltage control unit provides a power voltage. Pull-up and pull-down driving signals are generated based on the power voltage. An output driver generates an internal voltage according to the pull-up and pull-down driving signals. An active control unit controls drivability of the core voltage control unit in response to bank active signals.
摘要翻译：电压发生器通过选择性地驱动最终驱动器的控制晶体管来降低待机中的电流或自刷新模式的待机状态，并且缩短激活模式下的响应时间。核心电压控制单元提供电源电压。基于电源电压产生上拉和下拉驱动信号。输出驱动器根据上拉和下拉驱动信号产生内部电压。主动控制单元响应于行动信号控制核心电压控制单元的驾驶性能。

8. 发明申请

US20070050692A1 Test mode control circuit 失效
标题翻译：测试模式控制电路
公开(公告)号：US20070050692A1
公开(公告)日：2007-03-01
申请号：US11323382
申请日：2005-12-29
申请人： Ji-Eun Jang , Kee-Teok Park
发明人： Ji-Eun Jang , Kee-Teok Park
IPC分类号： G01R31/28
CPC分类号： G01R31/31701
摘要： Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated.
摘要翻译：提供了一种测试模式控制电路，其能够在测试模式进入之后防止在测试模式退出中的MRS（模式寄存器组）改变。在测试模式控制电路中，MRS控制器逻辑地组合MRS信号，存储体地址，MRS地址和测试模式控制信号以输出锁存控制信号。测试模式控制单元检测测试模式输入和测试模式退出以选择性地激活测试模式设置信号和测试模式退出信号之一，并且根据所述测试模式输入和测试模式退出信号的激活状态输出具有不同电压电平的测试模式控制信号测试模式设置信号或测试模式退出信号。当激活MRS信号时，地址锁存器锁存输入地址，并且当锁存控制信号被激活时，输出锁存的输入地址作为MRS地址。

9. 发明申请

US20050093590A1 Apparatus for generating power-up signal 失效
标题翻译：用于产生上电信号的装置
公开(公告)号：US20050093590A1
公开(公告)日：2005-05-05
申请号：US10875403
申请日：2004-06-25
申请人： Ji-Eun Jang
发明人： Ji-Eun Jang
IPC分类号： G11C7/00 , G11C5/14 , G11C7/20 , H03K5/153 , H03K17/22
CPC分类号： H03K17/223 , G11C5/143 , G11C7/20
摘要： An apparatus, included in a semiconductor memory device, for generating a power-up signal, including a first means for receiving a plurality of divided voltages and outputting a first control signal in response to a circumference temperature; and a signal generator for outputting the power-up signal in response to the first control signal.
摘要翻译：一种包括在半导体存储器件中的用于产生上电信号的装置，包括用于接收多个分压的第一装置，并响应于圆周温度输出第一控制信号; 以及信号发生器，用于响应于第一控制信号输出上电信号。

10. 发明授权

US08623473B2 Liquid crystal composition and liquid crystal display including the same 有权
标题翻译：液晶组成和液晶显示器包括相同
公开(公告)号：US08623473B2
公开(公告)日：2014-01-07
申请号：US13237783
申请日：2011-09-20
申请人： Si-Heun Kim , Seong-Nam Lee , Duck-Jong Suh , Ji-Eun Jang , Jae-Weon Hur
发明人： Si-Heun Kim , Seong-Nam Lee , Duck-Jong Suh , Ji-Eun Jang , Jae-Weon Hur
IPC分类号： C09K19/44 , C09K19/12 , C09K19/34 , C09K19/30
CPC分类号： C09K19/44 , C09K2019/0466 , C09K2019/123 , C09K2019/3016 , C09K2019/3025 , C09K2019/3422
摘要： A liquid crystal composition according to an exemplary embodiment of the present invention includes a liquid crystal compound represented by a below chemical formula (I) at about 10 wt % to about 15 wt %; and at least one liquid crystal compound at about 3 wt % to about 8 wt % among liquid crystal compounds represented by chemical formula (II) to chemical formula (IV). Here, X and Y may be equal to each other or different from each other, and each is an alkyl group or an alkenyl group having a carbon number of 1 to 4.
摘要翻译：根据本发明的示例性实施方案的液晶组合物包含以下述化学式（I）表示的液晶化合物：约10重量％至约15重量％和由化学式（II）表示为化学式（IV）的液晶化合物中的至少一种液晶化合物为约3重量％至约8重量％。这里，X和Y可以彼此相同或不同，并且各自为碳数为1〜4的烷基或烯基。

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