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1. 发明申请

US20120218838A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120218838A1
公开(公告)日：2012-08-30
申请号：US13100906
申请日：2011-05-04
申请人： Young-Jun Ku , Ki-Ho Kim
发明人： Young-Jun Ku , Ki-Ho Kim
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C29/26 , G11C7/1006 , G11C29/08 , G11C29/40 , G11C2029/2602
摘要： A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device.
摘要翻译：半导体存储器件包括：读出电路，被配置为在测试模式期间顺序地输出对应于待测试的所有存储体的多个压缩数据，以及在测试模式期间读取使能信号;以及衬垫，从读出电路依次输出到半导体存储器件的外部的压缩数据。

2. 发明申请

US20110292745A1 DATA TRANSMISSION DEVICE 有权
标题翻译：数据传输设备
公开(公告)号：US20110292745A1
公开(公告)日：2011-12-01
申请号：US12947298
申请日：2010-11-16
申请人： Young Jun KU
发明人： Young Jun KU
IPC分类号： G11C29/00 , G11C7/10
CPC分类号： G11C29/48 , G11C29/1201
摘要： A data transmission device in a semiconductor memory apparatus receives input data via a local data input/output line and output s the input data on a plurality of global data input/output lines. The data transmission device includes a write data generation block configured to receive the input data and test data and output one of input data and test data as write data in response to an activation of a test enable signal, and a loading block configured to apply the write data to one of the plurality of global data input/output lines in response to an enable signal.
摘要翻译：半导体存储装置中的数据传输装置经由本地数据输入/输出线接收输入数据，并输出多个全局数据输入/输出线上的输入数据。数据传输装置包括写数据生成块，其被配置为响应于激活测试使能信号而接收输入数据和测试数据并输出输入数据和测试数据之一作为写入数据;以及加载块，响应于使能信号将数据写入多个全局数据输入/输出线中的一个。

3. 发明授权

US08036053B2 Semiconductor memory device capable of suppressing a coupling effect of a test-disable transmission line 有权
标题翻译：能够抑制测试禁止传输线的耦合效应的半导体存储器件
公开(公告)号：US08036053B2
公开(公告)日：2011-10-11
申请号：US12134865
申请日：2008-06-06
申请人： Jeong-Yoon Ahn , Ji-Eun Jang , Young-Jun Ku
发明人： Jeong-Yoon Ahn , Ji-Eun Jang , Young-Jun Ku
IPC分类号： G11C29/00
CPC分类号： G11C29/46 , G11C29/02 , G11C29/025 , G11C29/1201 , G11C2029/1206
摘要： Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-mode control units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal.
摘要翻译：半导体器件和半导体存储器件包括多个内部电路，其被配置为响应于它们各自的测试模式信号执行测试操作;以及多个测试模式控制单元，被配置为响应于所述内部电路被禁用而控制内部电路的测试操作一个测试信号。

4. 发明申请

US20110128072A1 REPAIR CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权
标题翻译：维修电路和半导体器件包括它们
公开(公告)号：US20110128072A1
公开(公告)日：2011-06-02
申请号：US12836443
申请日：2010-07-14
申请人： Min Seok CHOI , Young Jun Ku
发明人： Min Seok CHOI , Young Jun Ku
IPC分类号： H01L25/00
CPC分类号： H01L22/22 , G06F2213/0038 , H01L23/481 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： A repair circuit of a semiconductor apparatus includes a transmission control unit configured to generate first through nth (n is an integer equal to or greater than 2) control signals in response to a repair information signal, and enable all mth through nth control signals when the repair information signal indicating an mth (m is an integer equal to or greater than 1 and equal to or less than n) TSV is inputted; transmission units configured to allocate transmission paths for first through nth signals to first through nth TSVs and a repair TSV in response to the first through nth control signals; and receiving units configured to receive the signals transmitted from the first through nth TSVs and the repair TSV in response to the first through nth control signals.
摘要翻译：半导体装置的修复电路包括发送控制单元，被配置为响应于修复信息信号产生第一至第n（n是等于或大于2的整数）控制信号，并且当第二至第N控制信号输入指示第m（m为1以上且等于或小于n的整数）TSV的修复信息信号; 传输单元，被配置为响应于第一至第N控制信号，将第一到第n个信号的传输路径分配到第一到第n个TSV和修复TSV; 以及接收单元，被配置为响应于第一至第N控制信号接收从第一至第TSV和修复TSV发送的信号。

5. 发明授权

US07940096B2 Register controlled delay locked loop circuit 失效
标题翻译：寄存器控制延迟锁定环路电路
公开(公告)号：US07940096B2
公开(公告)日：2011-05-10
申请号：US12337562
申请日：2008-12-17
申请人： Young-Jun Ku
发明人： Young-Jun Ku
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0818
摘要： A register controlled DLL circuit occupies a relatively small area in a semiconductor device by reducing the number of flip-flops for generating timing pulses that are used to control a DLL operation and sequentially toggled. The registered controlled DLL circuit for generating a DLL clock by delaying internal clocks includes a timing pre-pulse generating unit configured to generate a plurality of timing pre-pulses activated sequentially in response to a source clock, the plurality of pre-pulses being repeated two or more times in each delay shifting update period, a mask signal generating unit configured to generating a mask signal having a logic level varied according to toggling of a predetermined one of the timing pre-pulses, and a timing pulse outputting unit configured to output the plurality of timing pre-pulses as a plurality of timing pulses in response to the mask signal.
摘要翻译：寄存器控制DLL电路通过减少用于产生用于控制DLL操作并顺序切换的定时脉冲的触发器的数量，在半导体器件中占据相对较小的面积。用于通过延迟内部时钟产生DLL时钟的注册控制DLL电路包括：定时预脉冲生成单元，被配置为产生响应源时钟顺序激活的多个定时预脉冲，多个预脉冲重复两次在每个延迟移位更新周期中多个时间，掩模信号产生单元，其被配置为产生具有根据预定的一个定时预脉冲的切换而变化的逻辑电平的屏蔽信号;以及定时脉冲输出单元，多个定时预脉冲作为响应于掩模信号的多个定时脉冲。

6. 发明授权

US07915934B2 Delay locked loop circuit and operational method thereof 失效
标题翻译：延迟锁定环路电路及其操作方法
公开(公告)号：US07915934B2
公开(公告)日：2011-03-29
申请号：US12427028
申请日：2009-04-21
申请人： Young-Jun Ku
发明人： Young-Jun Ku
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： A delay locked loop circuit includes a clock buffering block to generate first and second internal clocks corresponding to first and second edges of a source clock in response to a clock buffering control signal, respectively, wherein generation of the second internal clock is controlled by a duty correcting operation terminating signal and a delay locking signal, a delay locking block to compare phases of the first and second internal clocks with those of first and second feedback clocks, respectively, to enable the delay locking signal according to a delay locking and delay the first and second internal clocks as many as times corresponding to the comparison results, respectively, thereby outputting first and second delay locking clocks, a duty correcting block to mix phases of the first and second delay locking clocks, and a first signal generating block to generate the duty correcting operation terminating signal.
摘要翻译：延迟锁定环电路包括时钟缓冲块，用于分别响应于时钟缓冲控制信号产生对应于源时钟的第一和第二边缘的第一和第二内部时钟，其中第二内部时钟的产生由占空比校正操作终止信号和延迟锁定信号，延迟锁定块，用于分别比较第一和第二内部时钟的相位与第一和第二反馈时钟的相位，以便根据延迟锁定实现延迟锁定信号，并延迟第一和第二内部时钟，分别对应于比较结果，由此输出第一和第二延迟锁定时钟，占空比校正块以混合第一和第二延迟锁定时钟的相位，以及第一信号生成块，以产生负载校正操作终止信号。

7. 发明授权

US07777542B2 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US07777542B2
公开(公告)日：2010-08-17
申请号：US11646105
申请日：2006-12-27
申请人： Young-Jun Ku
发明人： Young-Jun Ku
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required, or a smaller delay amount than a minimum delay amount of delay line is required. A control unit resets the delay locked loop according to the state of the delay line.
摘要翻译：半导体存储器件包括延迟锁定环，用于通过校正参考时钟和内部延迟时钟之间的相位差来实现延迟锁定状态，并且用于指示需要比延迟线的最大延迟量更大的延迟量的状态或者需要比延迟线的最小延迟量更小的延迟量。控制单元根据延迟线的状态复位延迟锁定环。

8. 发明授权

US07706199B2 Circuit and method for parallel test of memory device 失效
标题翻译：存储器件并行测试电路及方法
公开(公告)号：US07706199B2
公开(公告)日：2010-04-27
申请号：US12000123
申请日：2007-12-10
申请人： Young-Jun Ku , Kee-Teok Park
发明人： Young-Jun Ku , Kee-Teok Park
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , G11C2029/2602
摘要： A test circuit in a memory device includes a first compression unit configured to compress data of a plurality of cells to transmit first compressed data to a plurality of input/output lines, and a second compression unit configured to compress the first compressed data on the plurality of input/output line to output second compressed data to at least one output pin, wherein the second compression unit operates in a low compressing mode and a high compressing mode in response to a data compression selecting signal.
摘要翻译：存储器件中的测试电路包括：第一压缩单元，被配置为压缩多个单元的数据以将第一压缩数据发送到多个输入/输出线;以及第二压缩单元，被配置为压缩多个单元上的第一压缩数据输出/输出线以将第二压缩数据输出到至少一个输出引脚，其中响应于数据压缩选择信号，第二压缩单元以低压缩模式和高压缩模式操作。

9. 发明申请

US20080136476A1 Delay locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US20080136476A1
公开(公告)日：2008-06-12
申请号：US11646105
申请日：2006-12-27
申请人： Young-Jun Ku
发明人： Young-Jun Ku
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required, or a smaller delay amount than a minimum delay amount of delay line is required. A control unit resets the delay locked loop according to the state of the delay line.
摘要翻译：半导体存储器件包括延迟锁定环，用于通过校正参考时钟和内部延迟时钟之间的相位差来实现延迟锁定状态，并且用于指示需要比延迟线的最大延迟量更大的延迟量的状态或者需要比延迟线的最小延迟量更小的延迟量。控制单元根据延迟线的状态复位延迟锁定环。

10. 发明申请

US20070069783A1 Delay locked loop in synchronous semiconductor memory device and driving method thereof 有权
标题翻译：同步半导体存储器件中的延迟锁定环及其驱动方法
公开(公告)号：US20070069783A1
公开(公告)日：2007-03-29
申请号：US11528644
申请日：2006-09-28
申请人： Young-Jun Ku , Seok-Cheol Yoon
发明人： Young-Jun Ku , Seok-Cheol Yoon
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , G11C7/1072 , G11C7/222 , H03L7/0805
摘要： A semiconductor memory device including a delay locked loop can minimize current consumption during a precharge power down mode. The delay locked loop includes a buffer control block for generating a clock buffer enable signal in response to first and second signals, wherein the first signal represents a precharge power down mode and the second signal represents a reset of the delay locked loop, a clock buffering block, controlled by the clock buffer enable signal, for buffering an external clock to generate a reference clock, and a feedback loop for delaying the reference clock until a delay locking state to thereby output a DLL output clock.
摘要翻译：包括延迟锁定环路的半导体存储器件可以使预充电掉电模式期间的电流消耗最小化。延迟锁定环包括缓冲器控制块，用于响应于第一和第二信号产生时钟缓冲器使能信号，其中第一信号表示预充电掉电模式，第二信号表示延迟锁定环的复位，时钟缓冲由时钟缓冲器使能信号控制，用于缓冲外部时钟以产生参考时钟，以及用于延迟参考时钟直到延迟锁定状态从而输出DLL输出时钟的反馈回路。

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