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1. 发明授权

US06836849B2 Method and apparatus for controlling power and performance in a multiprocessing system according to customer level operational requirements 有权
标题翻译：根据客户级操作要求，在多处理系统中控制功率和性能的方法和装置
公开(公告)号：US06836849B2
公开(公告)日：2004-12-28
申请号：US09826986
申请日：2001-04-05
申请人： Bishop Chapman Brock , Harm Peter Hofstee , Mark A. Johnson , Thomas Walter Keller, Jr. , Kevin John Nowka
发明人： Bishop Chapman Brock , Harm Peter Hofstee , Mark A. Johnson , Thomas Walter Keller, Jr. , Kevin John Nowka
IPC分类号： G06F126
CPC分类号： G06F1/3203
摘要： A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system. Then controller generates controls and applies them to individual processors to achieve the performance goals.
摘要翻译：描述了一种用于管理多处理器（MP）系统的功率和性能的方法和控制器。控制器接收与MP系统内的物理参数对应的传感器数据。控制器还接收与MP系统对应的服务质量和策略参数。服务质量参数定义了对客户使用MP系统的承诺。策略参数对应于MP系统的输入和输出的操作限制。操作输入限制涉及功率或单个处理器可用性的成本和可用性。操作输出限制涉及允许MP系统中的个体或一组处理器在特定环境中生成的热量，声学噪声水平，EMC等级等。控制器接收物理参数，服务质量参数和策略参数，并确定MP系统中的MP系统和处理器的性能目标。然后控制器生成控件并将其应用于各个处理器以实现性能目标。

2. 发明授权

US06212619B1 System and method for high-speed register renaming by counting 失效
标题翻译：通过计数高速寄存器重命名的系统和方法，使用具有飞行中每条指令的寄存器位的表
公开(公告)号：US06212619B1
公开(公告)日：2001-04-03
申请号：US09075918
申请日：1998-05-11
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G06F1500
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A superscalar computer architecture for executing instructions out-of-order, comprising a multiplicity of execution units, a plurality of registers, and a register renaming circuit which generates a list of tags corresponding to specific registers that are not in use during loading of a given instruction. A table is constructed having one bit for each register per instruction in flight. The entries in the table may be combined in a logical OR fashion to create a vector that identifies which registers are in use by instructions that are in flight. Validity bits can also be generated to indicate validity of the generated tags, wherein a generated tag is invalid only if an insufficient number of registers are available during loading of the given instruction. The execution units are preferably pipelined.
摘要翻译：一种用于执行无序指令的超标量计算机体系结构，包括多个执行单元，多个寄存器和寄存器重命名电路，该电路生成与给定的加载期间不使用的特定寄存器相对应的标签列表指令。在飞行中每个指令的每个寄存器构造一个表。表中的条目可以以逻辑或或者方式组合，以创建一个向量，用于识别正在飞行中的指令使用哪些寄存器。也可以生成有效位以指示生成的标签的有效性，其中仅当在给定指令的加载期间没有足够数量的寄存器可用时，所生成的标签才是无效的。执行单元优选地被流水线化。

3. 发明授权

US6014763A At-speed scan testing 失效
标题翻译：高速扫描测试
公开(公告)号：US6014763A
公开(公告)日：2000-01-11
申请号：US7670
申请日：1998-01-15
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G01R31/28
CPC分类号： G01R31/318572
摘要： A method of scanning an integrated circuit, by converting a parallel scan input (scan data and scan control) to serial, passing the serial scan input through scan circuitry to create a serial scan output, converting the scan output from serial to parallel, transmitting the scan output in parallel from the integrated circuit to the tester. A tester clock signal is derived by synchronizing the tester to a divided clock signal (1/N) of the integrated circuit. Communications take place at a speed of the tester clock signal, but the scan operates at the full operational speed of the device under test. At-speed scan testing can be achieved for speeds in excess of 1 GHz.
摘要翻译：通过将并行扫描输入（扫描数据和扫描控制）转换为串行扫描来扫描集成电路的方法，将串行扫描输入通过扫描电路传送以创建串行扫描输出，将扫描输出从串行转换为并行转换，从集成电路并行扫描输出到测试仪。通过将测试仪与集成电路的分频时钟信号（1 / N）同步，得到测试仪时钟信号。通信以测试仪时钟信号的速度进行，但扫描以被测设备的全部操作速度运行。对于超过1 GHz的速度，可以实现高速扫描测试。

4. 发明授权

US06629235B1 Condition code register architecture for supporting multiple execution units 有权
标题翻译：用于支持多个执行单元的条件码寄存器架构
公开(公告)号：US06629235B1
公开(公告)日：2003-09-30
申请号：US09564943
申请日：2000-05-05
申请人： Brian King Flachs , Harm Peter Hofstee , Kevin John Nowka
发明人： Brian King Flachs , Harm Peter Hofstee , Kevin John Nowka
IPC分类号： G06F944
CPC分类号： G06F9/30094 , G06F9/3842
摘要： A condition code register architecture for supporting multiple execution units is disclosed. A master execution unit is coupled a master condition code register such that condition codes generated by the master execution unit are stored in the master condition code register. A non-master execution unit is coupled to a shadow condition code register such that condition codes generated by the non-master execution unit are stored in the shadow condition code register. A tag unit coupled to the master execution unit and the non-master execution unit such that an entry within the master condition code register can be read only when a corresponding entry within the tag unit is referenced to the master execution unit or the master condition code register.
摘要翻译：公开了一种用于支持多个执行单元的条件码寄存器架构。主执行单元耦合主状态代码寄存器，使得由主执行单元生成的条件代码被存储在主状态代码寄存器中。非主执行单元耦合到阴影条件代码寄存器，使得由非主执行单元生成的条件代码被存储在阴影条件代码寄存器中。耦合到主执行单元和非主执行单元的标签单元，使得只有在标签单元内的相应条目被引用到主执行单元或主条件代码时才能读取主条件代码寄存器内的条目寄存器。

5. 发明授权

US06598153B1 Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions 有权
标题翻译：加速评估条件设置和分支指令对的处理器和方法
公开(公告)号：US06598153B1
公开(公告)日：2003-07-22
申请号：US09458407
申请日：1999-12-10
申请人： Brian King Flachs , Harm Peter Hofstee , Kevin John Nowka
发明人： Brian King Flachs , Harm Peter Hofstee , Kevin John Nowka
IPC分类号： G06F938
CPC分类号： G06F9/30094 , G06F9/3842
摘要： A processor that promotes accelerated resolution of conditional branch instructions includes an instruction sequencer that fetches a plurality of instructions and a detector that detects, among the plurality of fetched instructions, a condition-setting instruction and a conditional branch instruction that depends upon the condition-setting instruction. The processor further includes a decoder that decodes the conditional branch instruction to produce a decoded condition type and an execution unit. In response to the detection of the condition-setting instruction and the conditional branch instruction, the execution unit resolves the conditional branch instruction by evaluating the condition-setting instruction and the decoded condition type in a single operation. Because the condition code bits are not computed or stored as an intermediate result as in prior art processors, branch resolution is accelerated.
摘要翻译：促进条件分支指令的加速分辨率的处理器包括取指定多个指令的指令定序器和检测器，其在多个取指令中检测条件设置指令和依赖于条件设置的条件转移指令指令。处理器还包括解码器，其解码条件分支指令以产生解码条件类型和执行单元。响应于条件设置指令和条件转移指令的检测，执行单元通过在单个操作中评估条件设置指令和解码条件类型来解析条件转移指令。由于条件码比特不像现有技术的处理器那样计算或存储为中间结果，所以分支分辨率被加速。

6. 发明授权

US06335650B1 Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages 有权
标题翻译：用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置
公开(公告)号：US06335650B1
公开(公告)日：2002-01-01
申请号：US09670829
申请日：2000-09-28
申请人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K19/00384 , H03K19/018585 , H03K2005/0013
摘要： A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.
摘要翻译：公开了一种用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置。电压电平检测器和延迟装置耦合到能够在多个电源电压下工作的集成电路的关键定时电路。电压电平检测器检测集成电路正在工作的电源电压。当集成电路的工作电源电压从第一电压电平变化到第二电压电平时，电压电平检测器向延迟装置和当前增强电路发送信号，使得延迟装置和电流增强电路可以自动修改来自关键定时电路的输出信号的切换时间的延迟。

7. 发明授权

US08086865B2 Supplying cryptographic algorithm constants to a storage-constrained target 失效
标题翻译：将密码算法常量提供给存储受限目标
公开(公告)号：US08086865B2
公开(公告)日：2011-12-27
申请号：US12116258
申请日：2008-05-07
申请人： Daniel Alan Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
发明人： Daniel Alan Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
IPC分类号： H04L9/12
CPC分类号： H04L9/3242
摘要： The present invention provides for authenticating a message, A security function is performed upon the message, The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.
摘要翻译：本发明提供了对消息的认证，对该消息执行安全功能。该消息被发送到目标。安全功能的输出被发送到目标。至少有一个公认的常数被发送到目标。接收到的消息被认证为至少共享密钥，接收的公知常数，安全功能，接收到的消息和安全功能的输出的功能。如果目标接收到的安全功能的输出与至少作为接收到的消息的函数产生的输出相同，则所接收的已知常数，安全功能和共享密钥，消息和常数都不具有被改变了

8. 发明授权

US07890561B2 Random number generator 失效
标题翻译：随机数发生器
公开(公告)号：US07890561B2
公开(公告)日：2011-02-15
申请号：US11204402
申请日：2005-08-16
申请人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
发明人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
IPC分类号： G06F1/02 , G06F7/58
CPC分类号： G06F7/588 , H04L9/001 , H04L9/0869
摘要： A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.
摘要翻译：提供随机数生成器，方法和计算机程序产品用于产生随机数种子。振荡器阵列内的每个振荡器以不同的频率工作。每个振荡器的工作频率不是谐波相关的，使得在任何两个振荡器的频率之间不存在整数倍。在一个实施例中，振荡器阵列的输出连接到多输入锁存器。多输入锁存器还接收作为时钟信号的采样信号。时钟信号对振荡器阵列的输出采样，并且多输入锁存器与随机数确定逻辑（“RNDL”）一起为阵列内的每个振荡器产生数字输出（0或1）。 RNDL使用这些数字输出创建一个随机数字种子。

9. 发明申请

US20110019368A1 Silicon Carrier Structure and Method of Forming Same 有权
标题翻译：硅载体结构及其形成方法
公开(公告)号：US20110019368A1
公开(公告)日：2011-01-27
申请号：US12507591
申请日：2009-07-22
申请人： Paul Stephen Andry , Harm Peter Hofstee , George A. Katopis , John Ulrich Knickerbocker , Robert K. Montoye , Chirag S. Patel
发明人： Paul Stephen Andry , Harm Peter Hofstee , George A. Katopis , John Ulrich Knickerbocker , Robert K. Montoye , Chirag S. Patel
IPC分类号： H05K1/18 , C23F1/00
CPC分类号： H01L25/0655 , H01L23/147 , H01L23/60 , H01L25/0652 , H01L2224/16225 , H01L2924/10253 , H01L2924/157 , Y02T10/82 , H01L2924/00
摘要： A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.
摘要翻译：一种用于电子封装的硅载体结构包括基底，设置在基底基板上的硅载体衬底，设置在硅载体衬底上的存储芯片，设置在硅载体衬底上的微处理器芯片，设置在硅衬底上的输入/输出芯片硅载体衬底和设置在硅载体衬底上的时钟芯片。

10. 发明申请

US20090327728A1 Methods for Supplying Cryptographic Algorithm Constants to a Storage-Constrained Target 失效
标题翻译：向存储约束目标提供加密算法常数的方法
公开(公告)号：US20090327728A1
公开(公告)日：2009-12-31
申请号：US12116258
申请日：2008-05-07
申请人： Daniel Alan Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
发明人： Daniel Alan Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
IPC分类号： H04L9/32
CPC分类号： H04L9/3242
摘要： The present invention provides for authenticating a message. A security function is performed upon the message. The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.
摘要翻译：本发明提供用于认证消息。对消息执行安全功能。该消息被发送到目标。安全功能的输出被发送到目标。至少有一个公认的常数被发送到目标。接收到的消息被认证为至少共享密钥，接收的公知常数，安全功能，接收到的消息和安全功能的输出的功能。如果目标接收到的安全功能的输出与至少作为接收到的消息的函数产生的输出相同，则所接收的公知常数，安全功能和共享密钥，消息和常数都不具有被改变了

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