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1. 发明授权

US5844840A High voltage NMOS pass gate having supply range, area, and speed advantages 失效
标题翻译：具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5844840A
公开(公告)日：1998-12-01
申请号：US914543
申请日：1997-08-19
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
IPC分类号： G11C8/08 , G11C16/06
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译：根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压实际上驱动到字线上。根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。

2. 发明授权

US06262469B1 Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor 失效
标题翻译：用于具有浮置晶体管作为相应电容器的电容分压器中的电容器
公开(公告)号：US06262469B1
公开(公告)日：2001-07-17
申请号：US09047237
申请日：1998-03-25
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer
IPC分类号： H01L2900
CPC分类号： H01L29/94 , H01L27/0811 , H01L29/66189
摘要： A capacitor divider includes two capacitors coupled in series between two voltage sources. A first capacitor is a floating gate capacitor having one plate being the control gate of a floating gate transistor structure and the other plate being a source, drain, and channel region of the floating gate transistor structure. The capacitive divider has the advantage of having at least one floating gate capacitor, can be implemented in a voltage regulator, and works for a variety of voltages across the capacitors.
摘要翻译：电容器分压器包括两个电容器，它们串联在两个电压源之间。第一电容器是浮置栅极电容器，其中一个板是浮栅晶体管结构的控制栅极，另一个栅极是浮栅晶体管结构的源极，漏极和沟道区。电容分压器的优点是具有至少一个浮置栅极电容器，可以在电压调节器中实现，并且可以用于跨越电容器的各种电压。

3. 发明授权

US5999452A Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory 失效
标题翻译：双源多晶硅选择门结构和编程方法，利用单隧道氧化物进行NAND阵列闪存
公开(公告)号：US5999452A
公开(公告)日：1999-12-07
申请号：US63688
申请日：1998-04-21
申请人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译：串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。串联选择晶体管连接到NAND串中的最后一个晶体管。源选择晶体管连接到阵列Vss电源。为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

4. 发明授权

US5912489A Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory 失效
标题翻译：双源端多晶硅选择门结构利用单隧道氧化物用于NAND阵列闪存
公开(公告)号：US5912489A
公开(公告)日：1999-06-15
申请号：US940674
申请日：1997-09-30
申请人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译：串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。串联选择晶体管连接到NAND串中的最后一个晶体管。源选择晶体管连接到阵列Vss电源。为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

5. 发明授权

US5909396A High voltage NMOS pass gate having supply range, area, and speed advantages 有权
标题翻译：具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5909396A
公开(公告)日：1999-06-01
申请号：US127991
申请日：1998-08-03
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
IPC分类号： G11C8/08 , G11C16/06
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistor's threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译：根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管的阈值电压实际上驱动到字线上。根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。

6. 发明授权

US5852576A High voltage NMOS pass gate for integrated circuit with high voltage generator and flash non-volatile memory device having the pass gate 失效
标题翻译：具有高电压发生器的集成电路的高电压NMOS通过栅极和具有通过栅极的闪存非易失性存储器件
公开(公告)号：US5852576A
公开(公告)日：1998-12-22
申请号：US944904
申请日：1997-10-06
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Shoichi Kawamura , Michael Shingche Chung , Vincent C. Leung , Masaru Yano
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Shoichi Kawamura , Michael Shingche Chung , Vincent C. Leung , Masaru Yano
IPC分类号： G11C16/06 , G11C8/08 , G11C16/12 , G11C13/00
CPC分类号： G11C16/12 , G11C8/08
摘要： Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.
摘要翻译：两个NMOS升压晶体管的源极连接到高压输入端，而它们的漏极和栅极交叉连接。两个耦合电容器将两个交替相位时钟连接到两个交叉连接的升压晶体管的栅极。 NMOS传输晶体管的栅极连接到一个NMOS升压晶体管的漏极，其源极连接到高压输入，其漏极连接到输出。在一个实施例中，两个二极管连接的调节晶体管将升压晶体管的栅极连接到高电压输入。这些连接确保升压晶体管的栅极和传输晶体管的栅极不会达到高于高电压输入以上的一个阈值电压的电压。在另一个实施例中，两个放电晶体管的漏极连接到解码输入，其源极连接到升压晶体管的栅极，并且其栅极连接到正电源。通过将解码输入设置为零伏特，升压晶体管和传输晶体管的栅极处的电压保持在零伏特，从而禁止它们。在优选实施例中，调节晶体管和放电晶体管都包括在高压通栅中。

7. 发明授权

US5939928A Fast high voltage NMOS pass gate for integrated circuit with high voltage generator 失效
标题翻译：具有高压发生器的集成电路的快速高压NMOS通道
公开(公告)号：US5939928A
公开(公告)日：1999-08-17
申请号：US914196
申请日：1997-08-19
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer
IPC分类号： G11C5/14 , G11C8/08 , G11C16/12 , H03K17/16
CPC分类号： G11C16/12 , G11C5/145 , G11C8/08
摘要： In a high voltage pass gate suitable for use as a block decoder in a flash memory circuit, the boosting of the block decoder's internal nodes is performed using coupling capacitors and boost transistors which are decoupled from the high capacitance pass gate node. The block decoder uses three internal block decoder nodes. Each of the three nodes is held to ground by a corresponding discharge transistor when the block is unselected. Each of the three nodes of a selected block is discharged to a normal supply voltage by a corresponding diode-connected regulation transistor when the high voltage supply is turned off after a programming operation has finished. Each of the three nodes has a separate coupling capacitor associated with it. One of the nodes is connected to the gates of the high voltage pass transistors, this node has high capacitance. The remaining two nodes have relatively small coupling capacitors. These other two nodes are capacitively coupling during opposite phases of a clock, and one of them controls a boost transistor which charges the high capacitance pass gate node. Two embodiments are presented, one having one less transistor than the other.
摘要翻译：在适用于闪速存储器电路中的块解码器的高压通道中，使用从高电容通过栅极节点去耦的耦合电容器和升压晶体管来执行块解码器的内部节点的升压。块解码器使用三个内部块解码器节点。当块未被选择时，三个节点中的每一个被相应的放电晶体管保持接地。当编程操作完成后，当高压电源关闭时，所选块的三个节点中的每一个都通过相应的二极管连接的调节晶体管放电到正常的电源电压。三个节点中的每一个具有与其相关联的单独的耦合电容器。节点中的一个连接到高电压通过晶体管的栅极，该节点具有高电容。剩余的两个节点具有相对较小的耦合电容器。这些另外两个节点在时钟的相反相位期间电容耦合，并且其中一个节点控制对高电容通过门节点充电的升压晶体管。呈现了两个实施例，一个具有比另一个更少的晶体管。

8. 发明授权

US07076703B1 Method and system for defining a redundancy window around a particular column in a memory array 有权
标题翻译：用于在存储器阵列中的特定列周围定义冗余窗口的方法和系统
公开(公告)号：US07076703B1
公开(公告)日：2006-07-11
申请号：US10305700
申请日：2002-11-26
申请人： Binh Quang Le , Pau-Ling Chen
发明人： Binh Quang Le , Pau-Ling Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/804
摘要： A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.
摘要翻译：一种用于存储器冗余的方法，包括通常具有存储器单元的多个列（例如，位线）的存储器阵列，以及识别存储器阵列的特定（例如，有缺陷的）列，并进一步通过选择一个一组相邻列，包括有缺陷的列。所选列组中的列数可以等于耦合到存储器阵列的冗余阵列中的列数。冗余阵列用于存储否则将存储在冗余窗口中的存储器单元中的信息。所选择的组包括在缺陷列的一侧上的至少一个列和在缺陷列的另一侧上的另一个列。通常，有缺陷的列的每一侧将有多个列。

9. 发明授权

US06288951B1 Method and apparatus for continuously regulating a charge pump output voltage using a capacitor divider 有权
标题翻译：使用电容分压器连续调节电荷泵输出电压的方法和装置
公开(公告)号：US06288951B1
公开(公告)日：2001-09-11
申请号：US09675940
申请日：2000-09-29
申请人： Pau-Ling Chen , Binh Quang Le
发明人： Pau-Ling Chen , Binh Quang Le
IPC分类号： G11C700
CPC分类号： G11C5/145
摘要： A non-volatile memory and method for continuously regulating an output of a charge pump of the non-volatile memory for long periods of time at a target output voltage.
摘要翻译：一种非易失性存储器和方法，用于在目标输出电压下长时间持续地调节非易失性存储器的电荷泵的输出。

10. 发明授权

US5995417A Scheme for page erase and erase verify in a non-volatile memory array 有权
标题翻译：在非易失性存储器阵列中进行页擦除和擦除验证的方案
公开(公告)号：US5995417A
公开(公告)日：1999-11-30
申请号：US175646
申请日：1998-10-20
申请人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
发明人： Pau-Ling Chen , Michael S. C. Chung , Shane C. Hollmer , Vincent Leung , Binh Quang Le , Masaru Yano
IPC分类号： G11C16/02 , G11C16/16 , G11C16/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.
摘要翻译：非易失性存储器件包括连接到各个字线16和18的多个MOS晶体管34和36，以允许存储在相应字线16和18上的存储器单元8a，10a和8b，10b中的存储器的各页被擦除和擦除验证。擦除一页存储单元的方法包括以下步骤：将擦除电压施加到MOS晶体管16和18中的一个以擦除沿着相应字线的存储单元的页面，并将初始擦除禁止浮动电压施加到其他连接到未选择用于页面擦除的字线的MOS晶体管。在擦除验证模式下，擦除验证电压被施加到在擦除模式下被选择用于页擦除的字线，并且擦除验证未选择电压被施加到未被选择用于页擦除的字线。

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