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1. 发明授权

US06370668B1 High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes 失效
标题翻译：高速存储器系统能够以非芯片杀死和芯片杀死模式选择性地运行
公开(公告)号：US06370668B1
公开(公告)日：2002-04-09
申请号：US09395160
申请日：1999-09-14
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G11C2900
CPC分类号： G06F11/1028 , G06F11/1044 , G11C7/1072
摘要： The present invention provides a high data bandwidth memory system capable of operating in non-chip-kill and chip-kill modes. In chip-kill mode, cycle multiplexing, bit multiplexing, and time and space multiplexing are used to read/write data and syndrome across a group of memory devices. Current command packet formats are adapted to communicate with the group of memory devices in chip-kill mode.
摘要翻译：本发明提供能够以非芯片杀死和芯片杀死模式操作的高数据带宽存储系统。在芯片杀死模式中，循环复用，位复用和时间和空间复用用于跨一组存储器件读/写数据和校正。当前命令分组格式适于以芯片杀死模式与该组存储器件进行通信。

2. 发明授权

US06839266B1 Memory module with offset data lines and bit line swizzle configuration 失效
标题翻译：具有偏移数据线和位线交错配置的内存模块
公开(公告)号：US06839266B1
公开(公告)日：2005-01-04
申请号：US10101243
申请日：2002-03-20
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G06F11/10 , G11C7/10 , G11C29/00 , G06F13/40
CPC分类号： G06F11/1028 , G06F11/1044 , G11C7/1072
摘要： A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.

3. 发明授权

US06708248B1 Memory system with channel multiplexing of multiple memory devices 失效
公开(公告)号：US06708248B1
公开(公告)日：2004-03-16
申请号：US09457155
申请日：1999-12-08
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G06F1200
CPC分类号： G06F13/1657 , G06F13/1684 , Y02D10/14
摘要： A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

4. 发明授权

US07039782B2 Memory system with channel multiplexing of multiple memory devices 失效
标题翻译：具有多个存储器件通道复用的存储器系统
公开(公告)号：US07039782B2
公开(公告)日：2006-05-02
申请号：US10690402
申请日：2003-10-20
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1684 , Y02D10/14
摘要： A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.
摘要翻译：公开了一种高速存储器系统，其中单个命令根据当前的操作模式对单个存储器件或多个存储器件进行控制。这种控制可以影响一个或多个存储器件与存储器控制器之间的数据传输，以及存储器件的操作状态转换或功率模式转换。类似地，相对低带宽的存储器件的各种配置作为有选择地控制的组进行响应以发送或接收高带宽数据。

5. 发明授权

US06681288B2 Memory device with receives write masking information 失效
标题翻译：接收写入掩蔽信息的存储器件
公开(公告)号：US06681288B2
公开(公告)日：2004-01-20
申请号：US10147931
申请日：2002-05-17
申请人： Frederick Abbott Ware , Craig Edward Hampel , Donald Charles Stark , Matthew Murdy Griffin
发明人： Frederick Abbott Ware , Craig Edward Hampel , Donald Charles Stark , Matthew Murdy Griffin
IPC分类号： G06F1202
CPC分类号： G11C7/22
摘要： A semiconductor memory device that includes an array of memory cells, the memory device operating synchronously with respect to an external clock signal. The memory device includes a set of interface terminals to receive a plurality of control signals which specify that the memory device receive a first set of data bits and a second set of data bits. The first set of data bits are received during a first half of a first clock cycle of the external clock signal. The second set of data bits are received during a second half of the first clock cycle of the external clock signal. In addition, the memory device includes a mask terminal to receive first and second mask bits during a second clock cycle of the external clock signal. The first clock cycle is temporally offset from the second clock cycle. The first mask bit is received during a first half of the second clock cycle, the first mask bit to indicate whether to write the first set of data bits to the array. The second mask bit is received during a second half of the second clock cycle, the second mask bit to indicate whether to write the second set of data bits to the array.
摘要翻译：一种包括存储器单元阵列的半导体存储器件，所述存储器件相对于外部时钟信号同步工作。存储器件包括一组接口端子，用于接收指定存储器件接收第一组数据位和第二组数据位的多个控制信号。第一组数据位在外部时钟信号的第一时钟周期的前半段期间被接收。第二组数据位在外部时钟信号的第一个时钟周期的后半段被接收。此外，存储器件包括在外部时钟信号的第二时钟周期期间接收第一和第二屏蔽位的掩码端子。第一个时钟周期在时间上偏离第二个时钟周期。第一个屏蔽位在第二个时钟周期的前一半期间被接收，第一个屏蔽位指示是否将第一组数据位写入阵列。在第二时钟周期的后半段期间接收第二掩码位，第二掩码位指示是否将第二组数据位写入阵列。

6. 发明授权

US06493789B2 Memory device which receives write masking and automatic precharge information 失效
标题翻译：接收写入屏蔽和自动预充电信息的存储器件
公开(公告)号：US06493789B2
公开(公告)日：2002-12-10
申请号：US09966126
申请日：2001-09-28
申请人： Frederick Abbott Ware , Craig Edward Hampel , Donald Charles Stark , Matthew Murdy Griffin
发明人： Frederick Abbott Ware , Craig Edward Hampel , Donald Charles Stark , Matthew Murdy Griffin
IPC分类号： G06F1202
CPC分类号： G11C7/22
摘要： A semiconductor memory device which includes a set of interface terminals to receive a plurality of control signals which specify that the memory device receive a first set of data bits and a second set of data bits. The plurality of control signals further specify that the memory device precharge sense amplifiers used in writing the first set of data bits to an array of memory cells, and precharge sense amplifiers used in writing the second set of data bits to the array of memory cells. The memory device further includes a mask terminal to receive a first mask bit during a first half of a clock cycle of an external clock signal, the first mask bit to indicate whether to write the first set of data bits to the array. The mask terminal further receives a second mask bit during a second half of the clock cycle of the external clock signal, the second mask bit to indicate whether to write the second set of data bits to the array.
摘要翻译：一种半导体存储器件，包括一组接口端子，用于接收指定存储器件接收第一组数据位和第二组数据位的多个控制信号。多个控制信号还指定用于将第一组数据位写入存储器单元阵列的存储器件预充电读出放大器，以及用于将第二组数据位写入存储器单元阵列的预充电读出放大器。存储器件还包括掩模终端，用于在外部时钟信号的时钟周期的前半部分期间接收第一掩码位，第一掩码位指示是否将第一组数据位写入阵列。掩模终端还在外部时钟信号的时钟周期的后半段期间接收第二掩码位，第二掩码位指示是否将第二组数据位写入阵列。

7. 发明授权

US06912620B2 Memory device which receives write masking information 失效
标题翻译：接收写入掩蔽信息的存储器件
公开(公告)号：US06912620B2
公开(公告)日：2005-06-28
申请号：US10686318
申请日：2003-10-15
申请人： Frederick Abbott Ware , Craig Edward Hampel , Donald Charles Stark , Matthew Murdy Griffin
发明人： Frederick Abbott Ware , Craig Edward Hampel , Donald Charles Stark , Matthew Murdy Griffin
IPC分类号： G11C11/413 , G11C7/22 , G11C11/401 , G06F12/00
CPC分类号： G11C7/22
摘要： A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory. A memory is also described with an array for data storage, a plurality of data input pins, and a separate pin for receiving either additional data or a serial sequence of write enable signals applicable to data received by the plurality of data input pins. The additional data that the separate pin can receive includes, for example, error detection and correction (EDC) information. A method is also described for multiplexing write enable information and error detection and correction information.
摘要翻译：描述了一种用于向存储器提供相对于由存储器的多个数据输入接收的相应数据在时间上偏移的写使能信号的串行序列的存储器。还描述了一种用于数据存储的阵列，多个数据输入引脚和用于接收适用于由多个数据输入引脚接收的数据的附加数据或可写入使能信号的串行序列的单独引脚的存储器。单独引脚可以接收的附加数据包括例如错误检测和校正（EDC）信息。还描述了一种用于复用写使能信息和错误检测和校正信息的方法。

8. 发明授权

US06496897B2 Semiconductor memory device which receives write masking information 失效
标题翻译：接收写入掩蔽信息的半导体存储器件
公开(公告)号：US06496897B2
公开(公告)日：2002-12-17
申请号：US09859097
申请日：2001-05-14
申请人： Frederick Abbott Ware , Craig Edward Hampel , Donald Charles Stark , Matthew Murdy Griffin
发明人： Frederick Abbott Ware , Craig Edward Hampel , Donald Charles Stark , Matthew Murdy Griffin
IPC分类号： G06F1202
CPC分类号： G11C7/22
摘要： A semiconductor memory device and a method of operation in the semiconductor memory device. The memory device receives an external clock signal and includes an array of memory cells. The method of operation of the memory device includes receiving, during a first half of a clock cycle of the external clock signal, a first data value and a first mask bit. The first mask bit indicates whether to write the first data value to the array. The method further includes receiving, during a second half of the clock cycle of the external clock signal, a second data value and a second mask bit. The second mask bit indicates whether to write the second data value to the array.
摘要翻译：半导体存储器件和半导体存储器件中的操作方法。存储器件接收外部时钟信号并且包括存储器单元阵列。存储器件的操作方法包括在外部时钟信号的时钟周期的前半段期间接收第一数据值和第一掩码位。第一个掩码位指示是否将第一个数据值写入数组。该方法还包括在外部时钟信号的时钟周期的后半段期间接收第二数据值和第二屏蔽位。第二个掩码位指示是否将第二个数据值写入数组。

9. 发明授权

US06266737B1 Method and apparatus for providing a memory with write enable information 失效
公开(公告)号：US06266737B1
公开(公告)日：2001-07-24
申请号：US09480825
申请日：2000-01-10
申请人： Frederick Abbott Ware , Craig Edward Hampel , Donald Charles Stark , Matthew Murdy Griffin
发明人： Frederick Abbott Ware , Craig Edward Hampel , Donald Charles Stark , Matthew Murdy Griffin
IPC分类号： G06F1202
CPC分类号： G11C7/22
摘要： A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory. A memory is also described with an array for data storage, a plurality of data input pins, and a separate pin for receiving either additional data or a serial sequence of write enable signals applicable to data received by the plurality of data input pins. The additional data that the separate pin can receive includes, for example, error detection and correction (EDC) information. A method is also described for multiplexing write enable information and error detection and correction information.

10. 发明申请

US20120201089A1 INTEGRATED CIRCUIT DEVICE COMPRISES AN INTERFACE TO TRANSMIT A FIRST CODE, A STROBE SIGNAL AFTER A DELAY AND DATA TO A DYNAMIC RANDOM ACCESS MEMORY (DRAM) 审中-公开
标题翻译：集成电路设备包含传输第一代码的接口，延迟和数据到动态随机存取存储器（DRAM）之后的结构信号
公开(公告)号：US20120201089A1
公开(公告)日：2012-08-09
申请号：US13451252
申请日：2012-04-19
申请人： Richard Maurice Barth , Frederick Abbott Ware , John Bradly Dillon , Donald Charles Stark , Craig Edward Hampel , Matthew Murdy Griffin
发明人： Richard Maurice Barth , Frederick Abbott Ware , John Bradly Dillon , Donald Charles Stark , Craig Edward Hampel , Matthew Murdy Griffin
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G06F13/161 , G11C5/066 , G11C7/10 , G11C7/1072 , G11C7/109 , G11C7/22 , G11C8/12 , G11C11/4076 , G11C11/4096
摘要： An integrated circuit device comprises an interface to transmit a first code, a strobe signal after a delay and data to a dynamic random access memory (DRAM). The first code indicates that data is to be written to the DRAM. The first code is registered by the DRAM on one or more edges of an external clock signal received by the DRAM. The strobe signal specifies one or more discrete points in time synchronous with the external clock signal at which the data is registered by the DRAM.
摘要翻译：集成电路装置包括用于传输第一代码的接口，延迟之后的选通信号和数据到动态随机存取存储器（DRAM）。第一个代码表示数据要写入DRAM。第一代码由DRAM在由DRAM接收的外部时钟信号的一个或多个边缘上注册。选通信号指定与由DRAM记录数据的外部时钟信号同步的一个或多个时间离散点。

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