专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060277511A1 System and method for memory element characterization 有权
标题翻译：用于记忆元素表征的系统和方法
公开(公告)号：US20060277511A1
公开(公告)日：2006-12-07
申请号：US11142709
申请日：2005-06-01
申请人： Bhavna Agrawal , Peter Feldmann , Sani Nassif , Tomasz Nowicki , Grzegorz Swirszcz
发明人： Bhavna Agrawal , Peter Feldmann , Sani Nassif , Tomasz Nowicki , Grzegorz Swirszcz
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031
摘要： A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.
摘要翻译：用于分析存储元件的系统和方法包括使用模拟方法对存储器元件进行建模并确定存储元件的组件的组件响应特性。在存储元件的状态空间中计算安全区域，其表示稳定状态。执行瞬态分析以确定到达安全区域之一所需的路径和时间。基于到达安全区域之一所需的路径和时间，确定在该安全区域中放置相应状态的时钟波形或波形。

2. 发明申请

US20090192776A1 CHARGE-BASED CIRCUIT ANALYSIS 有权
标题翻译：基于费率的电路分析
公开(公告)号：US20090192776A1
公开(公告)日：2009-07-30
申请号：US12163318
申请日：2008-06-27
申请人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven G. Walker
发明人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven G. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over a set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.
摘要翻译：提供了使用初始电荷信息分析电路的解决方案。特别地，用于电路的设计中的一个或多个节点用初始电荷初始化。电荷可以包括非平衡电荷，从而模拟历史效应，带电粒子的影响，静电放电（ESD）等。然后基于初始电荷在一组输入周期上模拟电路的操作。在这种程度上，非平衡初始条件解决方案使得能够控制电路的状态并且基于这些值来解决初始系统。该功能对于在最坏情况，最佳情况和/或类似状态下调节电路非常有用。此外，在本发明的一个实施例中，提供一组方程以实现非平衡初始电荷分析，其提供电路比当前解决方案更有效的初始化。

3. 发明授权

US07519526B2 Charge-based circuit analysis 失效
标题翻译：充电电路分析
公开(公告)号：US07519526B2
公开(公告)日：2009-04-14
申请号：US11355342
申请日：2006-02-16
申请人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven G. Walker
发明人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven G. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over the set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.
摘要翻译：提供了使用初始电荷信息分析电路的解决方案。特别地，用于电路的设计中的一个或多个节点用初始电荷初始化。电荷可以包括非平衡电荷，从而模拟历史效应，带电粒子的影响，静电放电（ESD）等。然后基于初始充电在该组输入周期上模拟电路的操作。在这种程度上，非平衡初始条件解决方案使得能够控制电路的状态并且基于这些值来解决初始系统。该功能对于在最坏情况，最佳情况和/或类似状态下调节电路非常有用。此外，在本发明的一个实施例中，提供一组方程以实现非平衡初始电荷分析，其提供电路比当前解决方案更有效的初始化。

4. 发明申请

US20070225958A1 Charge-based circuit analysis 失效
标题翻译：充电电路分析
公开(公告)号：US20070225958A1
公开(公告)日：2007-09-27
申请号：US11355342
申请日：2006-02-16
申请人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven Walker
发明人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over the set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.
摘要翻译：提供了使用初始电荷信息分析电路的解决方案。特别地，用于电路的设计中的一个或多个节点用初始电荷初始化。电荷可以包括非平衡电荷，从而模拟历史效应，带电粒子的影响，静电放电（ESD）等。然后基于初始充电在该组输入周期上模拟电路的操作。在这种程度上，非平衡初始条件解决方案使得能够控制电路的状态并且基于这些值来解决初始系统。该功能对于在最坏情况，最佳情况和/或类似状态下调节电路非常有用。此外，在本发明的一个实施例中，提供一组方程以实现非平衡初始电荷分析，其提供电路比当前解决方案更有效的初始化。

5. 发明授权

US08290760B2 Charge-based circuit analysis 有权
标题翻译：充电电路分析
公开(公告)号：US08290760B2
公开(公告)日：2012-10-16
申请号：US12163318
申请日：2008-06-27
申请人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven G. Walker
发明人： Emrah Acar , Bhavna Agrawal , Peter Feldmann , Ying Liu , Steven G. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over a set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.
摘要翻译：提供了使用初始电荷信息分析电路的解决方案。特别地，用于电路的设计中的一个或多个节点用初始电荷初始化。电荷可以包括非平衡电荷，从而模拟历史效应，带电粒子的影响，静电放电（ESD）等。然后基于初始电荷在一组输入周期上模拟电路的操作。在这种程度上，非平衡初始条件解决方案使得能够控制电路的状态并且基于这些值来解决初始系统。该功能对于在最坏情况，最佳情况和/或类似状态下调节电路非常有用。此外，在本发明的一个实施例中，提供一组方程以实现非平衡初始电荷分析，其提供电路比当前解决方案更有效的初始化。

6. 发明申请

US20080155484A1 SYSTEM AND METHOD FOR MEMORY ELEMENT CHARACTERIZATION 审中-公开
标题翻译：用于记忆元素表征的系统和方法
公开(公告)号：US20080155484A1
公开(公告)日：2008-06-26
申请号：US12034811
申请日：2008-02-21
申请人： Bhavna Agrawal , Peter Feldmann , Sani R. Nassif , Tomasz J. Nowicki , Grzegorz Michal Swirszcz
发明人： Bhavna Agrawal , Peter Feldmann , Sani R. Nassif , Tomasz J. Nowicki , Grzegorz Michal Swirszcz
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031
摘要： A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.
摘要翻译：用于分析存储元件的系统和方法包括使用模拟方法对存储器元件进行建模并确定存储元件的组件的组件响应特性。在存储元件的状态空间中计算安全区域，其表示稳定状态。执行瞬态分析以确定到达安全区域之一所需的路径和时间。基于到达安全区域之一所需的路径和时间，确定在该安全区域中放置相应状态的时钟波形或波形。

7. 发明授权

US07350170B2 System and method for memory element characterization 有权
标题翻译：用于记忆元素表征的系统和方法
公开(公告)号：US07350170B2
公开(公告)日：2008-03-25
申请号：US11142709
申请日：2005-06-01
申请人： Bhavna Agrawal , Peter Feldmann , Sani R. Nassif , Tomasz J. Nowicki , Grzegorz Michal Swirszcz
发明人： Bhavna Agrawal , Peter Feldmann , Sani R. Nassif , Tomasz J. Nowicki , Grzegorz Michal Swirszcz
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031
摘要： A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.
摘要翻译：用于分析存储元件的系统和方法包括使用模拟方法对存储器元件进行建模并确定存储元件的组件的组件响应特性。在存储元件的状态空间中计算安全区域，其表示稳定状态。执行瞬态分析以确定到达安全区域之一所需的路径和时间。基于到达安全区域之一所需的路径和时间，确定在该安全区域中放置相应状态的时钟波形或波形。

8. 发明授权

US08463571B2 Performing reliability analysis of signal wires 失效
标题翻译：执行信号线的可靠性分析
公开(公告)号：US08463571B2
公开(公告)日：2013-06-11
申请号：US12944892
申请日：2010-11-12
申请人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
发明人： Soroush Abbaspour , Ayesha Akhter , Peter Feldmann , Joachim Keinert
IPC分类号： G06F19/00 , G01R19/00
CPC分类号： G06F17/5036
摘要： A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.
摘要翻译：计算机实现的系统，方法和存储设备模拟集成电路设计的网络模型中的周期性电压波形。然后，该方法确定由周期性电压波形产生的集成电路设计的网络的每个段中的合成电流值，并执行周期性电压波形的傅立叶变换以产生周期性电压波形的频域表示。频域表示包括多个傅立叶项，每个傅立叶项是基频的倍数的频率。接下来，该方法对多傅里叶项的每个频率进行所得到的电压的AC分析。 AC分析为每个网络的傅立叶项的每个频率提供电流值。这允许该方法基于AC分析来计算通过每个网络的均方根电流。然后，该方法确定网络的任何段的均方根电流是否超过电流限制，并且报告均方根电流超过电流极限的网络的任何段。

9. 发明授权

US08020129B2 Multiple voltage threshold timing analysis for a digital integrated circuit 有权
标题翻译：数字集成电路的多电压阈值时序分析
公开(公告)号：US08020129B2
公开(公告)日：2011-09-13
申请号：US12021723
申请日：2008-01-29
申请人： Soroush Abbaspour , Peter Feldmann
发明人： Soroush Abbaspour , Peter Feldmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.
摘要翻译：描述了用于对数字集成电路执行多个电压阈值时序分析的方法。在一个实施例中，存在多电压阈值时序分析工具，用于执行具有由互连电路加载的至少一个逻辑门的数字集成电路的多电压阈值时序分析。在该实施例中，表征数据检索部件被配置为获得描述所述至少一个逻辑门的驱动行为的表征数据。互连电路模型检索部件被配置为获得互连电路的模型。多电压阈值时序分析部件被配置为导出驱动点电压波形的交叉时间序列以在连续的电压阈值之间前进。多电压阈值时序分析部件还根据导出的交叉时间序列产生电压波形。

10. 发明授权

US07933751B2 Method, apparatus and computer program providing broadband preconditioning based on reduced coupling for numerical solvers 失效
标题翻译：方法，装置和计算机程序提供基于减数耦合的数值求解器的宽带预处理
公开(公告)号：US07933751B2
公开(公告)日：2011-04-26
申请号：US12192459
申请日：2008-08-15
申请人： Peter Feldmann , Jason D. Morsey , Barry J. Rubin
发明人： Peter Feldmann , Jason D. Morsey , Barry J. Rubin
IPC分类号： G06F17/50 , G06G7/48 , G06G7/50 , G06G7/62 , G01N15/08 , G01F7/00 , G01F17/00
CPC分类号： G06F17/12
摘要： This invention relates to computing numerical solutions of linear systems of equations, specifically to implementing preconditioning of the coefficient matrix of such a system. The preconditioning applies to any coefficient matrix, dense or sparse, based on the solutions of a physical problem of unknown functions, commonly referred to as basis or interpolation functions, where the basis function spans more then one mesh element. Examples of such linear systems can result from, as examples, an electromagnetic analysis of printed circuit boards or field scattering in radar applications, fluid mechanics and acoustics. A method and system to compute a preconditioner for a coefficient matrix A that is compatible with the linear system of equations that provides basis function support over at least two mesh elements. Coupling of the preconditioner between partitions of a portioned mesh representation is only through basis functions at the partition boundaries.
摘要翻译：本发明涉及计算线性方程组的数值解，具体涉及实现这种系统的系数矩阵的预处理。基于未知函数的物理问题的解决方案，通常称为基础函数或插值函数，其中基函数跨越多于一个网格元素，该预处理适用于任何密集或稀疏的系数矩阵。作为示例，这种线性系统的示例可以从印刷电路板的电磁分析或雷达应用中的场散射，流体力学和声学等方面得到。一种用于计算系数矩阵A的预处理器的方法和系统，该系数矩阵A与在至少两个网格元素上提供基函数支持的线性方程组兼容。分段网格表示的分区之间的预处理器的耦合仅通过分区边界处的基函数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式