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1. 发明授权

US06819178B2 Selectable single mode or differential mode operation in a single amplifier 有权
标题翻译：在单个放大器中可选择单模或差分模式操作
公开(公告)号：US06819178B2
公开(公告)日：2004-11-16
申请号：US10670546
申请日：2003-09-25
申请人： Bert G. Pihlstrom , Ronnie E. Owens , Barbara J. Duffner , Michael Richter , Ulrich Knoch
发明人： Bert G. Pihlstrom , Ronnie E. Owens , Barbara J. Duffner , Michael Richter , Ulrich Knoch
IPC分类号： H03F345
CPC分类号： H03F3/68 , H03F3/45183 , H03F3/72
摘要： A dual mode amplifier having single ended and differential ended modes of operation using only one set of output pads or terminals. The dual mode amplifier has two differential amplifiers, connected by coupling circuitry, each differential amplifier receiving a pair of differential input signals and having one output terminal. By activating and deactivating the coupling circuitry, the differential amplifiers can operate in two modes using the one set of output terminals. In the singled ended mode, the differential amplifiers operate independently, each converting the differential input signals to a singled ended output signal at their respective output terminals. In the differential mode, the differential amplifiers operate together to provide a pair of differential output signals at the output terminals based upon the pair of input signals.
摘要翻译：具有单端和差分端模式的双模放大器，仅使用一组输出焊盘或端子。双模放大器具有两个由耦合电路连接的差分放大器，每个差分放大器接收一对差分输入信号并具有一个输出端。通过激活和去激活耦合电路，差分放大器可以使用一组输出端子在两种模式下工作。在单端模式中，差分放大器独立地工作，每个差分放大器在其各自的输出端子将差分输入信号转换为单端输出信号。在差分模式中，差分放大器一起工作，以在输出端基于一对输入信号提供一对差分输出信号。

2. 发明授权

US06664851B1 Selectable single mode or differential mode operation in a single amplifier 失效
标题翻译：在单个放大器中可选择单模或差分模式操作
公开(公告)号：US06664851B1
公开(公告)日：2003-12-16
申请号：US10267434
申请日：2002-10-09
申请人： Bert G. Pihlstrom , Ronnie E. Owens , Barbara J. Duffner , Michael Richter , Ulrich Knoch
发明人： Bert G. Pihlstrom , Ronnie E. Owens , Barbara J. Duffner , Michael Richter , Ulrich Knoch
IPC分类号： H03F114
CPC分类号： H03F3/68 , H03F3/45183 , H03F3/72
摘要： A dual mode amplifier having single ended and differential ended modes of operation using only one set of output pads or terminals. The dual mode amplifier has two differential amplifiers, connected by coupling circuitry, each differential amplifier receiving a pair of differential input signals and having one output terminal. By activating and deactivating the coupling circuitry, the differential amplifiers can operate in two modes using the one set of output terminals. In the singled ended mode, the differential amplifiers operate independently, each converting the differential input signals to a singled ended output signal at their respective output terminals. In the differential mode, the differential amplifiers operate together to provide a pair of differential output signals at the output terminals based upon the pair of input signals.
摘要翻译：具有单端和差分端模式的双模放大器，仅使用一组输出焊盘或端子。双模放大器具有两个由耦合电路连接的差分放大器，每个差分放大器接收一对差分输入信号并具有一个输出端。通过激活和去激活耦合电路，差分放大器可以使用一组输出端子在两种模式下工作。在单端模式中，差分放大器独立地工作，每个差分放大器在其各自的输出端子将差分输入信号转换为单端输出信号。在差分模式中，差分放大器一起工作，以在输出端基于一对输入信号提供一对差分输出信号。

3. 发明授权

US5999028A Differential circuits with adjustable propagation timing 失效
标题翻译：差分电路具有可调传播时间
公开(公告)号：US5999028A
公开(公告)日：1999-12-07
申请号：US995886
申请日：1997-12-22
申请人： Ulrich Knoch , Thorsten Krueger , Barbara Duffner , Ronnie Owens , Charles Moore
发明人： Ulrich Knoch , Thorsten Krueger , Barbara Duffner , Ronnie Owens , Charles Moore
IPC分类号： H03K19/0944 , H03F3/45 , H03K5/24 , H03K5/12 , G06G7/10
CPC分类号： H03F3/45771 , H03F3/45479 , H03K5/2481 , H03F2203/45624 , H03F2203/45646 , H03F2203/45702
摘要： Described is a circuit for receiving a differential input signal at two substantially symmetrically built up current paths and for providing an output signal therefrom. At least one current path comprises means for adjusting the timing information of the input signal to the timing information of the output signal. The adjustment can be accomplished by modifying a voltage level in the respective current path until the timing information of the output signals at least substantially represents the timing information of the input signal, e.g. by modifying an impedance or a current in the respective current path. The adjusting of the timing information is executed by applying a defined input signal with a known timing information, comparing the timing information of the resulting output signal with the timing information of the input signal, and modifying at least one voltage level in at least one of the current paths until the timing information of the output and input signals at least substantially match.
摘要翻译：描述了一种用于在两个基本上对称构建的电流路径处接收差分输入信号并用于从其提供输出信号的电路。至少一个电流路径包括用于将输入信号的定时信息调整为输出信号的定时信息的装置。可以通过修改相应电流路径中的电压电平来实现调整，直到输出信号的定时信息至少基本上表示输入信号的定时信息，例如，通过修改各个电流路径中的阻抗或电流。通过用已知的定时信息应用定义的输入信号来执行定时信息的调整，将所得到的输出信号的定时信息与输入信号的定时信息进行比较，并修改至少一个电压电平直到输出和输入信号的定时信息至少基本匹配的电流路径。

4. 发明申请

US20130193993A1 METHOD AND APPARATUS FOR TESTING A DEVICE-UNDER-TEST 有权
标题翻译：用于测试设备下测试的方法和装置
公开(公告)号：US20130193993A1
公开(公告)日：2013-08-01
申请号：US13574573
申请日：2010-01-20
申请人： Gil Golov , Thomas Henkel , Ronald Larson , Ulrich Knoch
发明人： Gil Golov , Thomas Henkel , Ronald Larson , Ulrich Knoch
IPC分类号： G01R31/319
CPC分类号： G01R31/319 , G01R31/31907
摘要： A method for testing a device-under-test includes receiving, from at least one test channel circuit dedicated to communicate with an input/output pin of the device-under-test by means of at least one hardware resource, at least one logical control command describing a desired operation of the at least one hardware resource, and converting, by means of a resource controller, the at least one logical control command into at least one dedicated control command for the at least one hardware resource, wherein the at least one dedicated control command is adapted to be received by a physical implementation of the at least one hardware resource.
摘要翻译：一种用于测试被测器件的方法包括：从至少一个测试通道电路接收至少一个逻辑控制器，所述至少一个测试通道电路专用于通过至少一个硬件资源与待测器件的输入/输出引脚通信; 描述所述至少一个硬件资源的期望操作，以及通过资源控制器将所述至少一个逻辑控制命令转换成所述至少一个硬件资源的至少一个专用控制命令，其中所述至少一个专用控制命令适于由所述至少一个硬件资源的物理实现来接收。

5. 发明授权

US09274175B2 Method and apparatus for testing a device-under-test 有权
标题翻译：用于测试被测设备的方法和装置
公开(公告)号：US09274175B2
公开(公告)日：2016-03-01
申请号：US13574573
申请日：2010-01-20
申请人： Gil Golov , Thomas Henkel , Ronald Larson , Ulrich Knoch
发明人： Gil Golov , Thomas Henkel , Ronald Larson , Ulrich Knoch
IPC分类号： G01R31/319
CPC分类号： G01R31/319 , G01R31/31907
摘要： A method for testing a device-under-test includes receiving, from at least one test channel circuit dedicated to communicate with an input/output pin of the device-under-test by means of at least one hardware resource, at least one logical control command describing a desired operation of the at least one hardware resource, and converting, by means of a resource controller, the at least one logical control command into at least one dedicated control command for the at least one hardware resource, wherein the at least one dedicated control command is adapted to be received by a physical implementation of the at least one hardware resource.
摘要翻译：一种用于测试被测器件的方法包括：从至少一个测试通道电路接收至少一个逻辑控制器，所述至少一个测试通道电路专用于通过至少一个硬件资源与待测器件的输入/输出引脚通信; 描述所述至少一个硬件资源的期望操作，以及通过资源控制器将所述至少一个逻辑控制命令转换成所述至少一个硬件资源的至少一个专用控制命令，其中所述至少一个专用控制命令适于由所述至少一个硬件资源的物理实现来接收。

6. 发明授权

US06065144A Testing unit with testing information divided into redundancy-free information and redundancy information 失效
标题翻译：具有测试信息的测试单元分为无冗余信息和冗余信息
公开(公告)号：US06065144A
公开(公告)日：2000-05-16
申请号：US42442
申请日：1998-03-13
申请人： Ulrich Knoch
发明人： Ulrich Knoch
IPC分类号： G01R31/3183 , G01R31/00 , G01R31/319 , G01R31/28
CPC分类号： G01R31/31921
摘要： A circuit for applying a testing data to a DUT for testing the DUT comprises a buffer memory for receiving and buffering a redundancy-free information as information which is substantially free of redundancy but might also comprise some redundant information to a certain extent, a redundancy memory for storing a redundancy information as information comprising a certain amount of redundancy, and a processing unit for generating the testing data by processing the redundancy-free information in association with the redundancy information. Further, includes a method for applying a testing data to the DUT for testing the DUT includes the steps of receiving and buffering the redundancy-free information, fetching in accordance with the received redundancy-free information the redundancy information, and generating the testing data by processing the redundancy-free information in association with the redundancy information.
摘要翻译：用于将测试数据应用于DUT的用于测试DUT的电路包括缓冲存储器，用于接收和缓冲无冗余信息，作为基本上不存在冗余的信息，但也可能在一定程度上包括一些冗余信息，冗余存储器用于存储冗余信息作为包括一定量的冗余度的信息;以及处理单元，用于通过与冗余信息相关联地处理无冗余信息来生成测试数据。此外，还包括将测试数据应用于被测试用于测试DUT的方法，包括接收和缓冲无冗余信息的步骤，根据接收的无冗余信息取出冗余信息，并通过以下步骤生成测试数据：处理与冗余信息相关联的无冗余信息。

7. 发明授权

US5293079A Formatter circuit 失效
标题翻译：格式化电路
公开(公告)号：US5293079A
公开(公告)日：1994-03-08
申请号：US964772
申请日：1992-10-22
申请人： Ulrich Knoch
发明人： Ulrich Knoch
IPC分类号： G01R31/3183 , G01R31/319 , H03K3/037 , H03K5/13
CPC分类号： G01R31/31922 , G01R31/31919 , G01R31/31928 , H03K3/037
摘要： A formatter circuit for an integrated circuit tester comprises at least one edge-triggered toggle flip-flop, which may be constituted of an EXOR gate and a D flip-flop. This allows to build an event-driven formatter with broad flexibility and "change timing" capability. The basic toggle flip-flops may be cascaded by further EXOR gates, in order to perform more complex functions and to combine several data input signals or clock signals.
摘要翻译：用于集成电路测试器的格式器电路包括至少一个边缘触发的触发器，其可以由EXOR门和D触发器构成。这允许构建一个具有广泛灵活性和“改变时序”功能的事件驱动格式化程序。基本的触发触发器可以被另外的EXOR门级联，以便执行更复杂的功能并组合多个数据输入信号或时钟信号。

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