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1. 发明授权

US07395483B1 Method and apparatus for performing error-detection and error-correction 有权
标题翻译：用于执行错误检测和纠错的方法和装置
公开(公告)号：US07395483B1
公开(公告)日：2008-07-01
申请号：US10966083
申请日：2004-10-15
申请人： Bernard Tourancheau , Ronald Ho , Robert J. Drost
发明人： Bernard Tourancheau , Ronald Ho , Robert J. Drost
IPC分类号： H03M13/37
CPC分类号： H03M13/09 , H03M13/098 , H03M13/2906
摘要： One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway. The system also receives a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet. As the data packet is received, the system performs an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet. Finally, the system compares the generated per-bit error-information with the corresponding per-bit error information in the time signature t to determine if there exists an error.
摘要翻译：本发明的一个实施例提供一种便于检测和纠正错误的系统。该系统通过在通信路径上接收由p个字组成的数据分组来进行操作，其中单词的每个比特在包含通信路径的一组数据线中的单独的数据线上被接收。系统还在通信路径上接收时间签名t，其中t包含数据包中的p个字的每位错误信息。当接收到数据包时，系统并行对数据包的每个数据位执行错误检测操作，其中错误检测操作针对数据包中的p个字的每个比特位置生成每位错误信息。最后，系统将生成的每位错误信息与时间签名t中相应的每位错误信息进行比较，以确定是否存在错误。

2. 发明授权

US07716393B2 Network chip design for grid communication 有权
标题翻译：电网通信网络芯片设计
公开(公告)号：US07716393B2
公开(公告)日：2010-05-11
申请号：US11148495
申请日：2005-06-09
申请人： Xavier-Francois Vigouroux , Bernard Tourancheau , Cedric Koch-Hofer
发明人： Xavier-Francois Vigouroux , Bernard Tourancheau , Cedric Koch-Hofer
IPC分类号： H01L23/00
CPC分类号： H01L23/48 , H01L23/49838 , H01L25/0652 , H01L2924/0002 , H04B5/0012 , H01L2924/00
摘要： A system includes a plurality of integrated circuits for propagating data between at least one central processing unit and another component of the system. The plurality of integrated circuits are configured for proximity I/O communication. The plurality of integrated circuits is configured such that data propagation through the plurality of integrated circuits is unaffected by a rotation of at least one of the plurality of integrated circuits by 90 degrees.
摘要翻译：一种系统包括用于在至少一个中央处理单元和系统的另一个组件之间传播数据的多个集成电路。多个集成电路被配置用于接近I / O通信。多个集成电路被配置为使得通过多个集成电路的数据传播不受多个集成电路中的至少一个的旋转90度的影响。

3. 发明授权

US07656805B2 Optimal communication path routing in a system employing interconnected integrated circuit technology 有权
标题翻译：采用互连集成电路技术的系统中的最优通信路径路由
公开(公告)号：US07656805B2
公开(公告)日：2010-02-02
申请号：US11219153
申请日：2005-09-02
申请人： Xavier-Francois Vigouroux , Bernard Tourancheau , Cedric Koch-Hofer
发明人： Xavier-Francois Vigouroux , Bernard Tourancheau , Cedric Koch-Hofer
IPC分类号： G01R31/08 , G06F15/173 , G06F17/20
CPC分类号： H04L45/122 , H04L45/06
摘要： An electronic system in which integrated circuits employing cornered I/O are arranged in a framework including an optional path manager and at least one updateable routing table. Packet routing options are described with solutions being provided to minimize transmission latency and pathway alternatives.
摘要翻译：一种电子系统，其中采用角化I / O的集成电路被布置在包括可选路径管理器和至少一个可更新路由表的框架中。使用提供的解决方案来描述数据包路由选项，以最小化传输延迟和路由选择。

4. 发明授权

US07444424B1 Method and apparatus for routing data across an n-dimensional grid network 有权
标题翻译：用于在n维网格网络中路由数据的方法和装置
公开(公告)号：US07444424B1
公开(公告)日：2008-10-28
申请号：US10674939
申请日：2003-09-29
申请人： Bernard Tourancheau
发明人： Bernard Tourancheau
IPC分类号： G06F15/173 , G06F17/50
CPC分类号： G06F17/5077 , G06F15/17337 , G06F17/5045 , H04L45/06
摘要： One embodiment of the present invention provides a system for routing data between integrated circuit devices. This system couples together an n-dimensional grid of integrated circuit devices using multiple independent communication networks, wherein each of the communication networks only moves data in two orthogonal directions (e.g., North and East, North and West, South and East, or South and West). The system also includes a routing mechanism that routes data across these communication networks, as well as, into, out of, and through integrated circuits within the n-dimensional grid of integrated circuits. Note that the process of routing a signal across a given network is greatly simplified because it is not possible to create a cycle that causes a deadlock within a given network.
摘要翻译：本发明的一个实施例提供了一种用于在集成电路设备之间路由数据的系统。该系统使用多个独立通信网络将n维集成电路设备网格耦合在一起，其中每个通信网络仅在两个正交方向上移动数据（例如，北，东，北，西，南，东或南，西）。该系统还包括路由机制，其跨越这些通信网络以及集成电路的n维网格内的集成电路以及通过集成电路路由数据。请注意，通过给定网络路由信号的过程大大简化，因为不可能创建引起给定网络内的死锁的周期。

5. 发明授权

US07191422B1 System and method for determining a carrier layout using cornered chip-to-chip input/output 有权
标题翻译：使用角码片对输入/输出确定载波布局的系统和方法
公开(公告)号：US07191422B1
公开(公告)日：2007-03-13
申请号：US10853936
申请日：2004-05-26
申请人： Bernard Tourancheau , Xavier-Francois Vigouroux , Cedric Koch-Hofer
发明人： Bernard Tourancheau , Xavier-Francois Vigouroux , Cedric Koch-Hofer
IPC分类号： G06F17/50
CPC分类号： H04L45/122 , H04L45/06
摘要： A system and method for determining a carrier layout using cornered chip-to-chip input/output is presented. Each of a plurality of individual integrated circuit carriers communicatively interfaceable through cornered input/output ports is oriented at a uniform rotation relative to an edge of a carrier layout. Each carrier defines a set of rectilinear edges. Each carrier is placed juxtaposed at an open corner to at least one other carrier within a rectilinear lattice topologically arranged in the carrier layout to substantially minimize Hamming distances between each of the carriers.
摘要翻译：提出了一种使用角码对芯片输入/输出确定载波布局的系统和方法。通过角部输入/输出端口可通信地接口的多个单独的集成电路载体中的每一个相对于载体布局的边缘被定向成均匀的旋转。每个载体定义一组直线边缘。每个载体被放置在敞开的角落处，并入布置在载体布局中的直线格架内的至少一个其它载体，以便基本上最小化每个载体之间的汉明距离。

6. 发明申请

US20060018261A1 Optimal communication path routing in a system employing interconnected integrated circuit technology 有权
标题翻译：采用互连集成电路技术的系统中的最优通信路径路由
公开(公告)号：US20060018261A1
公开(公告)日：2006-01-26
申请号：US11219153
申请日：2005-09-02
申请人： Xavier-Francois Vigouroux , Bernard Tourancheau , Cedric Koch-Hofer
发明人： Xavier-Francois Vigouroux , Bernard Tourancheau , Cedric Koch-Hofer
IPC分类号： H04J3/14 , G01R31/08
CPC分类号： H04L45/122 , H04L45/06
摘要： An electronic system is described in which integrated circuits employing cornered I/O are arranged in a framework including an optional path manager and at least one updateable routing table. Packet routing options are described with solutions being provided to minimize transmission latency and pathway alternatives.
摘要翻译：描述了一种电子系统，其中采用角度I / O的集成电路被布置在包括可选路径管理器和至少一个可更新路由表的框架中。使用提供的解决方案来描述数据包路由选项，以最小化传输延迟和路由选择。

7. 发明授权

US07561584B1 Implementation of a graph property in a switching fabric for fast networking 有权
标题翻译：在交换架构中实现图形属性，实现快速联网
公开(公告)号：US07561584B1
公开(公告)日：2009-07-14
申请号：US11270010
申请日：2005-11-09
申请人： Bernard Tourancheau , Henri Gouraud , Danny Cohen , Ivan Sutherland
发明人： Bernard Tourancheau , Henri Gouraud , Danny Cohen , Ivan Sutherland
IPC分类号： H04L12/28 , G06F15/173
CPC分类号： H04L49/25 , H04L49/10
摘要： A system, including at least one central processing unit, at least one memory unit, and a plurality of integrated circuits that form a switching fabric configured to propagate data packets between the at least one central processing unit and the at least one memory unit, wherein the switching fabric is constructed using at least two directed acyclic graph (DAG) networks.
摘要翻译：一种系统，包括至少一个中央处理单元，至少一个存储器单元和多个集成电路，其形成配置成在所述至少一个中央处理单元和所述至少一个存储器单元之间传播数据分组的交换结构，其中交换结构使用至少两个有向无环图（DAG）网络构建。

8. 发明授权

US07352741B2 Method and apparatus for speculative arbitration 有权
标题翻译：投机性仲裁的方法和手段
公开(公告)号：US07352741B2
公开(公告)日：2008-04-01
申请号：US10080135
申请日：2002-02-21
申请人： Hans Eberle , Nils Gura , Nicolas Fugier , Bernard Tourancheau
发明人： Hans Eberle , Nils Gura , Nicolas Fugier , Bernard Tourancheau
IPC分类号： H04L12/28 , G06F13/14 , H04L12/403
CPC分类号： H04L49/254 , H04L12/40019 , H04L12/4015 , H04L12/407 , H04L47/15 , H04L47/50 , H04L49/201 , H04L49/206 , H04L49/253 , H04L49/30 , H04W72/04
摘要： An arbiter is used so multiple users can use shared resources. The arbiter allocates at least one of the resources speculatively to one of the users for use during a particular access interval in the absence of a request for the resource from the user. The arbiter can also allocate one or more of the resources for use during the particular access interval in response to requests received by the arbiter for the resource(s). That is, a particular access interval may include both speculative and non-speculative allocation of resources by the arbiter.
摘要翻译：使用仲裁器，因此多个用户可以使用共享资源。仲裁者在没有来自用户的资源的请求的情况下，在特定的访问间隔期间，将至少一个资源投机地分配给其中一个用户以供使用。仲裁器还可以响应于仲裁器为资源接收到的请求，在特定访问间隔期间分配一个或多个资源以供使用。也就是说，特定的访问间隔可以包括仲裁者的投机和非推测性资源分配。

9. 发明申请

US20060224796A1 Network chip design for grid communication 有权
标题翻译：电网通信网络芯片设计
公开(公告)号：US20060224796A1
公开(公告)日：2006-10-05
申请号：US11148495
申请日：2005-06-09
申请人： Xavier-Francois Vigouroux , Bernard Tourancheau , Cedric Koch-Hofer
发明人： Xavier-Francois Vigouroux , Bernard Tourancheau , Cedric Koch-Hofer
IPC分类号： G06F13/38
CPC分类号： H01L23/48 , H01L23/49838 , H01L25/0652 , H01L2924/0002 , H04B5/0012 , H01L2924/00
摘要： A system includes a plurality of integrated circuits for propagating data between at least one central processing unit and another component of the system. The plurality of integrated circuits are configured for proximity I/O communication. The plurality of integrated circuits is configured such that data propagation through the plurality of integrated circuits is unaffected by a rotation of at least one of the plurality of integrated circuits by 90 degrees.
摘要翻译：一种系统包括用于在至少一个中央处理单元和系统的另一个组件之间传播数据的多个集成电路。多个集成电路被配置用于接近I / O通信。多个集成电路被配置为使得通过多个集成电路的数据传播不受多个集成电路中的至少一个的旋转90度的影响。

10. 发明授权

US07064583B1 Arbiters with preferential enables for asynchronous circuits 有权
标题翻译：具有优先权的仲裁器可以实现异步电路
公开(公告)号：US07064583B1
公开(公告)日：2006-06-20
申请号：US10922744
申请日：2004-08-19
申请人： Jo C. Ebergen , Ivan E. Sutherland , Bernard Tourancheau
发明人： Jo C. Ebergen , Ivan E. Sutherland , Bernard Tourancheau
IPC分类号： H03K19/20
CPC分类号： G06F13/14 , G06F13/364 , H03K3/356113 , H03K3/356147
摘要： One embodiment of the present invention provides a circuit that preferentially grants requests. This circuit monitors at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with a corresponding enable signal. If any enable signal is asserted and only one request signal is asserted, the circuit asserts a grant signal associated with the asserted request signal. Otherwise, if a single enable signal is asserted and multiple request signals are asserted, the circuit preferentially asserts the grant signal of the request signal associated with the asserted enable signal.
摘要翻译：本发明的一个实施例提供一种优先授权请求的电路。该电路监视至少两个用于请求信号的输入和用于使能信号的至少两个输入，其中每个请求信号与相应的使能信号相关联。如果任何使能信号被有效并且只有一个请求信号被断言，则电路断言与被断言的请求信号相关联的授权信号。否则，如果单个使能信号被断言并且多个请求信号被断言，则电路优先地断言与所述使能信号相关联的请求信号的授权信号。

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