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1. 发明授权

US07064583B1 Arbiters with preferential enables for asynchronous circuits 有权
标题翻译：具有优先权的仲裁器可以实现异步电路
公开(公告)号：US07064583B1
公开(公告)日：2006-06-20
申请号：US10922744
申请日：2004-08-19
申请人： Jo C. Ebergen , Ivan E. Sutherland , Bernard Tourancheau
发明人： Jo C. Ebergen , Ivan E. Sutherland , Bernard Tourancheau
IPC分类号： H03K19/20
CPC分类号： G06F13/14 , G06F13/364 , H03K3/356113 , H03K3/356147
摘要： One embodiment of the present invention provides a circuit that preferentially grants requests. This circuit monitors at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with a corresponding enable signal. If any enable signal is asserted and only one request signal is asserted, the circuit asserts a grant signal associated with the asserted request signal. Otherwise, if a single enable signal is asserted and multiple request signals are asserted, the circuit preferentially asserts the grant signal of the request signal associated with the asserted enable signal.
摘要翻译：本发明的一个实施例提供一种优先授权请求的电路。该电路监视至少两个用于请求信号的输入和用于使能信号的至少两个输入，其中每个请求信号与相应的使能信号相关联。如果任何使能信号被有效并且只有一个请求信号被断言，则电路断言与被断言的请求信号相关联的授权信号。否则，如果单个使能信号被断言并且多个请求信号被断言，则电路优先地断言与所述使能信号相关联的请求信号的授权信号。

2. 发明授权

US07636361B1 Apparatus and method for high-throughput asynchronous communication with flow control 有权
标题翻译：具有流量控制的高吞吐量异步通信的装置和方法
公开(公告)号：US07636361B1
公开(公告)日：2009-12-22
申请号：US11242113
申请日：2005-09-27
申请人： Jo C. Ebergen , Justin M. Schauer , Robert D. Hopkins , Ivan E. Sutherland
发明人： Jo C. Ebergen , Justin M. Schauer , Robert D. Hopkins , Ivan E. Sutherland
IPC分类号： H04L12/28
CPC分类号： H04L49/40
摘要： One embodiment of the present invention provides a system that asynchronously controls sending data items from a sender to a receiver. This system includes a set of sending FIFOs, a set of receiving FIFOs, as well as a shared data path between the sender and the receiver. The system also includes a set of control paths that operate in parallel between the sender and the receiver, wherein a given control path controls the transmission of data items between a corresponding sending FIFO and a corresponding receiving FIFO through the shared data path. The system further includes a round-robin scheduling mechanism which activates one control path at a time in a predetermined sequence. An activated control path asynchronously controls the sending of a data item from a corresponding sending FIFO to a corresponding receiving FIFO. By operating the control paths in parallel in the predetermined sequence, the system does not have to wait a request-acknowledge cycle time between the sender and the receiver before sending consecutive data items through the shared data path, but can instead send multiple data items through the shared data path within a single request-acknowledge cycle time.
摘要翻译：本发明的一个实施例提供了一种异步地控制从发送器到接收器发送数据项的系统。该系统包括一组发送FIFO，一组接收FIFO，以及发送器和接收器之间的共享数据路径。该系统还包括在发送器和接收器之间并行操作的一组控制路径，其中给定的控制路径通过共享数据路径来控制在对应的发送FIFO和对应的接收FIFO之间的数据项的传输。该系统还包括循环调度机制，其以预定的顺序一次激活一个控制路径。激活的控制路径异步地控制将数据项从相应的发送FIFO发送到相应的接收FIFO。通过以预定的顺序并行地操作控制路径，系统在发送连续数据项之前不必等待发送方和接收方之间的请求确认周期时间，而是可以通过共享数据路径发送多个数据项在单个请求确认周期时间内的共享数据路径。

3. 发明授权

US06753726B1 Apparatus and method for an offset-correcting sense amplifier 有权
公开(公告)号：US06753726B1
公开(公告)日：2004-06-22
申请号：US10356450
申请日：2003-01-31
申请人： Robert J. Drost , Ivan E. Sutherland
发明人： Robert J. Drost , Ivan E. Sutherland
IPC分类号： G06G712
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H03F1/301 , H03F1/342 , H01L2924/00
摘要： An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.

4. 发明授权

US06707317B2 Method and apparatus for asynchronously controlling domino logic gates 有权
标题翻译：用于异步控制多米诺逻辑门的方法和装置
公开(公告)号：US06707317B2
公开(公告)日：2004-03-16
申请号：US10135166
申请日：2002-04-29
申请人： Josephus C. Ebergen , Ivan E. Sutherland , Jon Lexau , Jonathan Gainsley
发明人： Josephus C. Ebergen , Ivan E. Sutherland , Jon Lexau , Jonathan Gainsley
IPC分类号： H03K19096
CPC分类号： H03K19/0966
摘要： One embodiment of the present invention provides a domino logic circuit that operates asynchronously. This domino logic circuit includes a number of stages, including a present stage that receives one or more inputs from a prior stage and generates one or more outputs for a next stage. It also includes a control circuit that ensures that the present stage enters a precharging state before entering a subsequent evaluation state in which one or more inputs of the present stage are used to generate one or more outputs. This control circuit receives a prior control signal from the prior stage and sends a present control signal to the next stage
摘要翻译：本发明的一个实施例提供了一种异步操作的多米诺逻辑电路。该多米诺骨牌逻辑电路包括多个级，包括从现有级接收一个或多个输入并为下一级生成一个或多个输出的当前级。它还包括控制电路，其确保当前级在进入后级评估状态之前进入预充电状态，其中使用当前级的一个或多个输入来产生一个或多个输出。该控制电路接收来自前一级的先前控制信号，并将当前控制信号发送到下一级

5. 发明授权

US06600325B2 Method and apparatus for probing an integrated circuit through capacitive coupling 有权
公开(公告)号：US06600325B2
公开(公告)日：2003-07-29
申请号：US09778622
申请日：2001-02-06
申请人： William S. Coates , Robert J. Bosnyak , Ivan E. Sutherland
发明人： William S. Coates , Robert J. Bosnyak , Ivan E. Sutherland
IPC分类号： G01R3108
CPC分类号： G01R31/303 , G01R31/3025 , G01R31/312
摘要： One embodiment of the present invention provides a system for capacitively probing electrical signals within an integrated circuit. This system operates by placing a probe conductor in close proximity to, but not touching, a target conductor within the integrated circuit. In this position, the probe conductor and the target conductor form a capacitor that stores a charge between the probe conductor and the target conductor. Next, the system detects a change in a probe voltage on the probe conductor caused by a change in a target voltage on the target conductor, and then determines a logic value for the target conductor based on the change in the probe voltage. In one embodiment of the present invention, determining the logic value for the target conductor involves, determining a first value if the probe voltage decreases, and determining a second value if the probe voltage increases.

6. 发明授权

US6072805A Observing arbiter 失效
标题翻译：观察仲裁者
公开(公告)号：US6072805A
公开(公告)日：2000-06-06
申请号：US884927
申请日：1997-06-30
申请人： Charles E. Molnar, deceased , Ian W. Jones , Ivan E. Sutherland
发明人： Charles E. Molnar, deceased , Ian W. Jones , Ivan E. Sutherland
IPC分类号： H04J3/02
CPC分类号： G06F13/364
摘要： An arbiter is disclosed for determining a sequence of signals indicative of events occurring variously on at least two input connections. The arbiter includes a first input connection and a second input connection for carrying the signals indicative of events. A first input queue for storing representations of events that are waiting to be processed is connected to the first input connection, and a second input queue also for storing representations of events that are waiting to be processed is connected to the second input connection. An arbitration circuit coupled to the first input queue and to the second input queue receives the representations of events from each of the queues and determines the temporal order of occurrence of the event representations in the queues when the events arrive at time intervals greater than a specified amount, and arbitrarily assigns a sequence to one or the other of the events from the queues when the events arrive at time intervals equal to or less than the specified amount. In response the arbitration circuit reports the temporal order or arbitrary sequence as a sequence of output signals and removes each event representation from the appropriate queue when reporting its temporal order or sequence.
摘要翻译：公开了一种用于确定指示在至少两个输入连接上不同地发生的事件的信号序列的仲裁器。仲裁器包括用于承载指示事件的信号的第一输入连接和第二输入连接。用于存储等待被处理的事件的表示的第一输入队列连接到第一输入连接，并且还用于存储等待被处理的事件的表示的第二输入队列连接到第二输入连接。耦合到第一输入队列和第二输入队列的仲裁电路从每个队列接收事件的表示，并且当事件以大于指定的时间间隔的时间间隔到达时，确定队列中的事件表示的出现的时间顺序量，并且当事件以等于或小于指定量的时间间隔到达时，将序列任意地分配给队列中的一个或另一个事件。作为响应，仲裁电路将时间顺序或任意序列报告为输出信号的序列，并在报告其时间顺序或序列时从适当的队列中移除每个事件表示。

7. 发明授权

US5861762A Inverse toggle XOR and XNOR circuit 失效
标题翻译：反转触发XOR和XNOR电路
公开(公告)号：US5861762A
公开(公告)日：1999-01-19
申请号：US813054
申请日：1997-03-07
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： H03K19/21 , H03K19/0948
CPC分类号： H03K19/215
摘要： A four transistor XOR or XNOR gate includes an inverting stage and a non-inverting stage. The transistors in each stage are coupled so as to enable changing inputs and existing inputs to drive the output in the same direction. The XOR gate and XNOR gate take advantage of a known order or inputs to reduce the delay of the gate.
摘要翻译：四极晶体管XOR或XNOR门包括反相级和非反相级。每个级中的晶体管被耦合，以便能够改变输入和现有输入以在相同方向上驱动输出。 XOR门和XNOR门利用已知的顺序或输入来减少门的延迟。

8. 发明授权

US4679213A Asynchronous queue system 失效
标题翻译：异步队列系统
公开(公告)号：US4679213A
公开(公告)日：1987-07-07
申请号：US689635
申请日：1985-01-08
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： G11C19/00 , H03K23/58
CPC分类号： G11C19/00
摘要： A queue form of asynchronous register is disclosed with signal paths commonly carrying elements of both data and control. Binaries are intercoupled in two sequences and are individually cross coupled to register "one" bits in one sequence and "zero" bits in the other. Bits are manifest by signal level changes. Individual binaries are driven by logic to accomplish an operational rule based on the states of neighboring binaries in both sequences. Each binary in each sequence is controlled by the states of the predecessor and successor in its sequence and the predecessor and successor of its associated binary in the other sequence. Specifically, if predecessor and successor binaries in a sequence are in different states, and predecessor and successor binaries of an associated binary in the other sequence are in the same state, the state of the predecessor is to be taken.
摘要翻译：披露了具有通常携带数据和控制元素的信号路径的异步寄存器的队列形式。二进制序列以两个序列相互配合，并且被单独交叉耦合以在一个序列中寄存“一个”比特，而在另一个序列中“零”比特。位由信号电平变化表现。单个二进制文件由逻辑驱动，以基于两个序列中的相邻二进制文件的状态来完成操作规则。每个序列中的每个二进制由其序列中的前导和后继的状态以及在其他序列中的相关二进制的前导和后继来控制。具体来说，如果序列中的前导和后继二进制文件处于不同的状态，并且其他序列中相关联的二进制文件的前导和后继二进制文件处于相同的状态，则将采用前导的状态。

9. 发明授权

US4209240A Reticle exposure apparatus and method 失效
标题翻译：光罩曝光装置及方法
公开(公告)号：US4209240A
公开(公告)日：1980-06-24
申请号：US949756
申请日：1978-10-10
申请人： Ivan E. Sutherland , Charles L. Seitz
发明人： Ivan E. Sutherland , Charles L. Seitz
IPC分类号： G03F7/20 , G03B41/00
CPC分类号： G03F7/704
摘要： An apparatus and method are described for applying a light beam in an extremely precise pattern to a work piece, such as a photographic plate or reticle on which an integrated circuit pattern is to be formed and which will be then utilized to produce integrated circuits. The method includes moving a very narrow beam light source relative to the reticle in a scanning pattern such as an X-Y raster pattern, accurately sensing the relative positions of the light source to the reticle as by the use of laser interferometers, and briefly energizing the light source only when it lies at the locations to be exposed. The light source is energized while it moves, so it is not necessary to stop the light source at precisely located positions. The light source can be moved relative to the reticle, by mounting the light source on a flexible plate that oscillates in substantially a straight line, and by mounting the reticle on another flexible plate that moves perpendicular to the light source and that can be very slowly advanced perpendicular to the oscillating light source, so that after a period of time the light source has moved over every point of the reticle, although only a minority of the points normally will have been exposed.
摘要翻译：描述了一种用于以非常精确的图案将光束施加到工件（例如要在其上形成集成电路图案的照相板或标线片）上并随后用于产生集成电路的装置和方法。该方法包括以诸如XY光栅图案的扫描图案相对于掩模版移动非常窄的光束光源，通过使用激光干涉仪精确地感测光源到掩模版的相对位置，并且短暂地激励光只有当它位于要暴露的位置时才能使用。光源在移动时被通电，因此不需要在精确定位的位置停止光源。光源可以通过将光源安装在基本上直线上振荡的柔性板上，并且通过将光罩安装在垂直于光源移动的另一柔性板上并且可以非常缓慢地相对于光罩移动垂直于振荡光源前进，使得在一段时间之后光源已经移动到标线的每个点上，尽管只有少数点通常将被曝光。

10. 发明申请

US20130080815A1 SYNCHRONIZING TIMING OF COMMUNICATION BETWEEN INTEGRATED CIRCUITS 有权
标题翻译：集成电路之间的通信同步时序
公开(公告)号：US20130080815A1
公开(公告)日：2013-03-28
申请号：US13239957
申请日：2011-09-22
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F3/00 , G06F5/06 , G06F13/42 , H03K19/00 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit includes a first pipeline with multiple stages of asynchronous circuits. Note that a stage in the first pipeline communicates with a stage in a corresponding second pipeline with multiple stages of asynchronous circuits on another integrated circuit via connectors. Furthermore, a first state wire preceding the stage in the first pipeline provides advanced notice to a first state wire preceding the stage in the second pipeline of subsequent communication between the stage in the first pipeline and the stage in the second pipeline so that the stage in the second pipeline has time to amplify a signal received from the stage in the first pipeline, thereby facilitating approximately synchronous operation of the stages in the first and second pipelines.
摘要翻译：集成电路包括具有多级异步电路的第一流水线。注意，第一流水线中的一级通过连接器与另一集成电路上的多级异步电路的相应的第二管线中的级通信。此外，第一管线中的级之前的第一状态线将第一管线中的级与第二管线中的级之间的后续通信的第二管道中的级之间的第一状态引线提前通知，第二管线有时间放大从第一管道中的级接收的信号，从而便于第一和第二管道中的级的大致同步操作。

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