专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5989997A Method for forming dual damascene structure 失效
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US5989997A
公开(公告)日：1999-11-23
申请号：US61659
申请日：1998-04-17
申请人： Benjamin Szu-Min Lin , Jason Jenq
发明人： Benjamin Szu-Min Lin , Jason Jenq
IPC分类号： H01L21/768 , H01L21/314
CPC分类号： H01L21/76808 , Y10S438/948
摘要： A method for forming dual damascene metallic structure that utilizes the formation of a protective photoresist layer at the bottom of a vertical window to prevent damages to a device region in the substrate when subsequent etching operation is carried out to form a horizontal trench pattern. The protective photoresist layer at the bottom of the vertical window is formed by irradiating the photoresist layer with a dose of radiation having energy level insufficient to chemically dissociate the photoactive molecules of the photoresist layer near the bottom of the vertical window.
摘要翻译：一种用于形成双镶嵌金属结构的方法，其利用在垂直窗口的底部形成保护光致抗蚀剂层，以防止当进行后续蚀刻操作以形成水平沟槽图案时对基板中的器件区域的损坏。垂直窗口底部的保护光致抗蚀剂层是通过用能量水平不足以化学解离靠近垂直窗口底部的光致抗蚀剂层的光活性分子的辐射照射光致抗蚀剂层而形成的。

2. 发明授权

US6159788A Method to increase DRAM cell capacitance 失效
标题翻译：增加DRAM单元电容的方法
公开(公告)号：US6159788A
公开(公告)日：2000-12-12
申请号：US975497
申请日：1997-11-21
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/84 , H01L27/10852
摘要： An electrode for a DRAM charge storage capacitor is provided with a textured surface using a wet etching process that has far greater process latitude and a lower cost than conventional processes for forming hemispherical grained silicon. A base capacitor electrode is provided for a DRAM cell preferably having a conventional polysilicon surface on which the textured surface will be formed. A layer of polycrystalline material having a composition different from the polysilicon surface is provided over the polysilicon surface. The layer of polycrystalline material is subjected to a wet etching process which preferentially etches along the grain boundaries of the layer of polycrystalline material. This wet etching process removes portions of the layer of polycrystalline material from over the polysilicon surface. The remaining portions of the layer of polycrystalline material are then used as a mask for etching the surface of the polysilicon, introducing a texture to the surface of the polysilicon layer. The surface of the polysilicon layer is then cleaned and a capacitor dielectric and upper capacitor electrode are provided over the textured polysilicon surface.
摘要翻译： DRAM电荷存储电容器的电极使用湿式蚀刻工艺提供纹理表面，其具有比用于形成半球形晶粒硅的常规工艺更大的工艺范围和更低的成本。为DRAM单元设置基极电容器电极，其优选地具有将形成纹理表面的常规多晶硅表面。在多晶硅表面上提供具有不同于多晶硅表面的组成的多晶材料层。对多晶材料层进行湿蚀刻工艺，其优先沿着多晶材料层的晶界蚀刻。这种湿蚀刻工艺从多晶硅表面上去除多晶材料层的部分。然后将多晶材料层的剩余部分用作蚀刻多晶硅表面的掩模，将纹理引入多晶硅层的表面。然后清洁多晶硅层的表面，并在纹理多晶硅表面上提供电容器电介质和上电容器电极。

3. 发明授权

US06114231A Wafer structure for securing bonding pads on integrated circuit chips and a method for fabricating the same 失效
标题翻译：用于固定集成电路芯片上的焊盘的晶片结构及其制造方法
公开(公告)号：US06114231A
公开(公告)日：2000-09-05
申请号：US691522
申请日：1996-08-02
申请人： Kun-Cho Chen , Jason Jenq
发明人： Kun-Cho Chen , Jason Jenq
IPC分类号： H01L21/768 , H01L23/485 , H01L21/44
CPC分类号： H01L24/02 , H01L21/76804 , H01L21/7684 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/04941 , H01L2924/14
摘要： A wafer structure on an IC chip allows the bonding pads on the IC chip to be firmly secured to the IC chip, thereby preventing detachment of the bonding pads during assembly of the IC package. The wafer structure comprises a substrate on which at least a pad area is defined. The pad area is formed with a first insulating layer, a gate on the first insulating layer, a second insulating layer on the gate, and a third insulating layer on the second insulating layer. The second insulating layer has a plurality of lower openings formed therethrough and the third insulating layer has a plurality of upper openings formed therethrough, each upper opening corresponding to one of the lower openings. The lower openings are wider than the upper openings. Plugs are formed in the lower and upper openings and are bonded to a metallization layer which serves as a bonding pad for the IC chip. The wider lower part of the plugs allows them to be rigidly affixed within the openings, thus allowing the overlaying bonding pad to be firmly secured to the IC chip. Therefore, during assembly of the IC chip, the bonding pad is not readily detached from the IC chip, thus increasing the assembly yield of good IC packages.
摘要翻译： IC芯片上的晶片结构允许IC芯片上的接合焊盘牢固地固定到IC芯片，从而防止在IC封装的组装过程中接合焊盘脱离。晶片结构包括其上限定了至少一个焊盘区域的衬底。焊盘区域形成有第一绝缘层，第一绝缘层上的栅极，栅极上的第二绝缘层和第二绝缘层上的第三绝缘层。第二绝缘层具有穿过其形成的多个下开口，第三绝缘层具有穿过其形成的多个上开口，每个上开口对应于一个下开口。下开口比上开口宽。插头形成在下开口和上开口中，并且与用作IC芯片的焊盘的金属化层接合。插头的较宽的下部允许它们刚性地固定在开口内，从而允许覆盖的焊盘牢固地固定在IC芯片上。因此，在组装IC芯片期间，接合焊盘不容易从IC芯片脱离，因此提高了IC封装的组装成品率。

4. 发明授权

US6030867A Method of fabricating a Fin/HSG DRAM cell capacitor 失效
标题翻译：制造Fin / HSG DRAM单元电容器的方法
公开(公告)号：US6030867A
公开(公告)日：2000-02-29
申请号：US975708
申请日：1997-11-21
申请人： Sun-Chieh Chien , Jason Jenq , Der-Yuan Wu , Chia-Wen Liang
发明人： Sun-Chieh Chien , Jason Jenq , Der-Yuan Wu , Chia-Wen Liang
IPC分类号： H01L21/02 , H01L21/60 , H01L21/768 , H01L21/8242
CPC分类号： H01L24/11 , H01L27/10852 , H01L28/84 , H01L21/76895 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： The DRAM cell is formed by covering the cell's transfer FET with a conformal insulating layer. A self aligned contact etch removes a portion of the conformal insulating layer from above a first source/drain region of the FET and then a first polysilicon layer is deposited over the device. Etching defines a polysilicon pad from the first polysilicon layer with edges of the polysilicon pad disposed over the gate electrode and an adjacent wiring line. A thick, planarized second insulating layer is provided over the device, filling the volume defined by the locally cupped surface of the polysilicon pad. Etching is performed to remove a portion of the planarized insulating layer using the pad polysilicon layer as an etch stop for the process. A second, thick polysilicon layer is next provided to fill the cavity and the layer is patterned to laterally define the lower capacitor electrode. Hemispherical grained silicon (HSG-Si) is deposited on the surface of the patterned polysilicon layer and an etch back process is used to transfer the topology of the HSG-Si layer to the underlying polysilicon. Further processing provides a capacitor dielectric and an upper electrode.
摘要翻译：通过用保形绝缘层覆盖电池的转移FET来形成DRAM单元。自对准接触蚀刻从FET的第一源极/漏极区上方去除保形绝缘层的一部分，然后在器件上沉积第一多晶硅层。蚀刻定义了来自第一多晶硅层的多晶硅焊盘，其中多晶硅焊盘的边缘设置在栅电极和相邻布线之上。在该器件上方提供厚的平坦化的第二绝缘层，填充由多晶硅垫的局部杯形表面限定的体积。使用焊盘多晶硅层作为该工艺的蚀刻停止来执行蚀刻以去除平坦化绝缘层的一部分。接下来提供第二厚的多晶硅层以填充空腔，并且对该层进行图案化以横向限定下部电容器电极。半球形晶粒硅（HSG-Si）沉积在图案化的多晶硅层的表面上，并且使用回蚀工艺将HSG-Si层的拓扑转移到下面的多晶硅。进一步的处理提供电容器电介质和上电极。

5. 发明授权

US5874335A Method of fabricating DRAM capacitors 失效
标题翻译：制造DRAM电容器的方法
公开(公告)号：US5874335A
公开(公告)日：1999-02-23
申请号：US27523
申请日：1998-02-23
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90
摘要： A method for fabricating a semiconductor device is provided comprising forming a dual silicon nitride spacer to be an etching step layer during a self-aligned contact etching step. The invention discloses a bottom electrode with a tri-forked structure and a hemispherical grain layer of a capacitor, therefore the capacitor has a larger surface area. So the capacitor made by the invention has a high capacitance even though the planar surface size is reduced continually.
摘要翻译：提供了一种制造半导体器件的方法，包括在自对准接触蚀刻步骤期间形成作为蚀刻步骤层的双重氮化硅间隔物。本发明公开了一种具有三叉结构的底电极和电容器的半球形晶粒层，因此电容器具有较大的表面积。因此，即使平面表面尺寸连续减小，本发明制成的电容器具有高电容。

6. 发明授权

US5795805A Fabricating method of dynamic random access memory 失效
标题翻译：动态随机存取存储器的制作方法
公开(公告)号：US5795805A
公开(公告)日：1998-08-18
申请号：US904543
申请日：1997-08-04
申请人： Der-Yuan Wu , Jason Jenq
发明人： Der-Yuan Wu , Jason Jenq
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A fabricating method of a dynamic random access memory is provided. The characteristic of the method is the formation of a dielectric layer to protect a polysilicon layer of hemispheric grains, and thus, the slurry residue from chemical-mechanical polishing process is avoided. In addition, the dielectric layer and the oxide layer can be removed by the same step of wet etching without an additional process. The exposure limitation is not restricted by the shrinkage of the devices. Therefore, the polysilicon layer of hemispherical grains can be removed precisely as expected.
摘要翻译：提供了一种动态随机存取存储器的制造方法。该方法的特征在于形成介电层以保护半球晶粒的多晶硅层，从而避免了化学机械抛光过程中的残留物。此外，可以通过相同的湿法蚀刻步骤除去电介质层和氧化物层，而无需额外的工艺。曝光限制不受设备收缩的限制。因此，半球形晶粒的多晶硅层可以按预期精确地去除。

7. 发明授权

US5989953A Method for manufacturing DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US5989953A
公开(公告)日：1999-11-23
申请号：US998599
申请日：1997-12-29
申请人： Chia-Wen Liang , Jason Jenq
发明人： Chia-Wen Liang , Jason Jenq
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for forming a DRAM capacitor that utilizes silicon nitride spacers on two occasions to perform self-aligned contact window etching operations. Furthermore, on the second etching operation, one less photomask is required for the etching of the second via. In addition, a silicon nitride layer over the first polysilicon layer has a smaller thickness than the usual oxide layer in a conventional method of manufacture. Consequently, a shallower contact step height for the capacitor, which is beneficial to the production of miniaturized devices, is obtained. Finally, the tri-fork shaped capacitor structure further increases the surface area of the capacitor so that the capacitance of the DRAM capacitor is increased.
摘要翻译：一种用于形成利用氮化硅间隔物两次的DRAM电容器进行自对准接触窗蚀刻操作的方法。此外，在第二蚀刻操作中，对于第二通孔的蚀刻需要少一个光掩模。此外，在常规的制造方法中，第一多晶硅层上的氮化硅层的厚度比通常的氧化物层厚。因此，获得有利于小型化装置的生产的电容器的较浅的接触台阶高度。最后，三叉形电容器结构进一步增加了电容器的表面积，使得DRAM电容器的电容增大。

8. 发明授权

US5981334A Method of fabricating DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US5981334A
公开(公告)日：1999-11-09
申请号：US965326
申请日：1997-11-06
申请人： Sun-Chieh Chien , Jason Jenq , C. C. Hsue
发明人： Sun-Chieh Chien , Jason Jenq , C. C. Hsue
IPC分类号： H01L21/02 , H01L21/70 , H01L21/00
CPC分类号： H01L28/82 , H01L28/84 , H01L28/91
摘要： A method for fabricating DRAM capacitor which includes forming a transistor having a source/drain regions and a gate electrode above a silicon substrate; then, forming sequentially a stack of layers including a first insulating layer, a second insulating layer, a third insulating layer and a hard mask layer over the transistor; subsequently, patterning and etching the hard mask layer. Thereafter, an oxide layer is formed over the hard mask layer, and then portions of the layers are etched to form a capacitor region over the oxide layer and a contact opening exposing a portion of the source/drain region. In the subsequent step, a conducting layer is formed over the oxide layer, the hard mask layer, the sidewalls of the contact opening and the exposed portion of the source/drain region. Next, a polishing method is used to remove the conducting layer above the oxide layer, and then the oxide layer is removed to form a lower electrode. A dielectric layer is then formed over the lower electrode, and finally an upper electrode layer is formed over the dielectric layer.
摘要翻译：一种用于制造DRAM电容器的方法，其包括在硅衬底上形成具有源极/漏极区域和栅极电极的晶体管; 然后在晶体管上依次形成包括第一绝缘层，第二绝缘层，第三绝缘层和硬掩模层的层叠层; 随后，对硬掩模层进行图案化和蚀刻。此后，在硬掩模层之上形成氧化物层，然后蚀刻这些层的一部分以在氧化物层上形成电容器区域，以及暴露源极/漏极区域的一部分的接触开口。在随后的步骤中，在氧化物层，硬掩模层，接触开口的侧壁和源极/漏极区域的暴露部分之上形成导电层。接下来，使用抛光方法去除氧化物层上方的导电层，然后除去氧化物层以形成下电极。然后在下电极上形成电介质层，最后在电介质层上形成上电极层。

9. 发明授权

US5960280A Method of fabricating a fin/cavity capacitor structure for DRAM cell 失效
标题翻译：制造用于DRAM单元的鳍/腔电容器结构的方法
公开(公告)号：US5960280A
公开(公告)日：1999-09-28
申请号：US975489
申请日：1997-11-21
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84
摘要： A DRAM is formed by providing a transfer FET, providing an elevated structure over and adjacent to the transfer FET and then forming a cavity above one of the source/drain regions of the transfer FET. The cavity is filled with a conductor to define in part a lower electrode of a charge storage capacitor. Portions of the cavity are then removed to expose additional charge storage surfaces for the lower electrode of the charge storage capacitor. The elevated structure includes a thick, planarized insulating layer provided over the transfer FET. A cavity is formed by providing an etching mask over the thick, planarized insulating layer with an opening positioned over the first source/drain. Etching is performed to remove a portion of the second insulating layer. A thick polysilicon layer is provided to fill the cavity and then the second, thick polysilicon layer is patterned to laterally define the lower capacitor electrode, preferably leaving portions of the second polysilicon layer extending above the stepped opening and onto surrounding portions of the second insulating layer. The second insulating layer is then removed to expose additional surfaces of the lower capacitor electrode for charge storage. Processing continues to provide a capacitor dielectric layer, an upper capacitor electrode and a bit line contact to complete the DRAM.
摘要翻译：通过提供转移FET来形成DRAM，在转移FET上方并且靠近转移FET，然后在转移FET的源极/漏极区之一上形成空腔。空腔填充有导体，部分地限定电荷存储电容器的下电极。然后去除腔的部分以暴露电荷存储电容器的下电极的附加电荷存储表面。升高的结构包括设置在转移FET上的厚的平坦化绝缘层。通过在厚的平坦化绝缘层上设置蚀刻掩模形成空腔，其中开口位于第一源极/漏极之上。执行蚀刻以去除第二绝缘层的一部分。提供厚多晶硅层以填充空腔，然后将第二厚多晶硅层图案化以横向限定下电容器电极，优选地使第二多晶硅层的部分在阶梯开口上方延伸到第二绝缘层的周围部分。然后去除第二绝缘层以露出用于电荷存储的下部电容器电极的附加表面。处理继续提供电容器介电层，上电容器电极和位线接触来完成DRAM。

10. 发明授权

US06153465A Method of fabricating a capacitor of dynamic random access memory 失效
标题翻译：制造动态随机存取存储器电容器的方法
公开(公告)号：US06153465A
公开(公告)日：2000-11-28
申请号：US8863
申请日：1998-01-20
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/84 , H01L27/10852
摘要： A method of fabricating a capacitor of a dynamic random access memory is provided. A substrate is first provided, wherein a first dielectric layer is formed on the substrate, and a via is formed through the first dielectric layer to expose one of source/drain regions. A conductive material is formed on the first dielectric layer so that the conductive material is filled in the via to contact with the one of the source/drain regions. The conductive material is patterned to form a first conductive layer. A hemispherical polysilicon grain layer is formed at least on the first conductive layer. The hemispherical polysilicon grain layer is etched back so that the first conductive layer and the hemispherical polysilicon grain layer together form a lower electrode. A second dielectric layer is formed on the lower electrode. A second conductive layer is formed on the second dielectric layer to be an upper electrode.
摘要翻译：提供一种制造动态随机存取存储器的电容器的方法。首先提供衬底，其中在衬底上形成第一电介质层，并且通过第一介电层形成通孔以暴露源/漏区之一。导电材料形成在第一电介质层上，使得导电材料填充在通孔中以与源/漏区之一接触。将导电材料图案化以形成第一导电层。至少在第一导电层上形成半球状多晶硅晶粒层。半球形多晶硅晶粒层被回蚀刻，使得第一导电层和半球形多晶硅晶粒层一起形成下电极。在下电极上形成第二电介质层。在第二电介质层上形成第二导电层作为上电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式