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1. 发明授权

US6159788A Method to increase DRAM cell capacitance 失效
标题翻译：增加DRAM单元电容的方法
公开(公告)号：US6159788A
公开(公告)日：2000-12-12
申请号：US975497
申请日：1997-11-21
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/84 , H01L27/10852
摘要： An electrode for a DRAM charge storage capacitor is provided with a textured surface using a wet etching process that has far greater process latitude and a lower cost than conventional processes for forming hemispherical grained silicon. A base capacitor electrode is provided for a DRAM cell preferably having a conventional polysilicon surface on which the textured surface will be formed. A layer of polycrystalline material having a composition different from the polysilicon surface is provided over the polysilicon surface. The layer of polycrystalline material is subjected to a wet etching process which preferentially etches along the grain boundaries of the layer of polycrystalline material. This wet etching process removes portions of the layer of polycrystalline material from over the polysilicon surface. The remaining portions of the layer of polycrystalline material are then used as a mask for etching the surface of the polysilicon, introducing a texture to the surface of the polysilicon layer. The surface of the polysilicon layer is then cleaned and a capacitor dielectric and upper capacitor electrode are provided over the textured polysilicon surface.
摘要翻译： DRAM电荷存储电容器的电极使用湿式蚀刻工艺提供纹理表面，其具有比用于形成半球形晶粒硅的常规工艺更大的工艺范围和更低的成本。为DRAM单元设置基极电容器电极，其优选地具有将形成纹理表面的常规多晶硅表面。在多晶硅表面上提供具有不同于多晶硅表面的组成的多晶材料层。对多晶材料层进行湿蚀刻工艺，其优先沿着多晶材料层的晶界蚀刻。这种湿蚀刻工艺从多晶硅表面上去除多晶材料层的部分。然后将多晶材料层的剩余部分用作蚀刻多晶硅表面的掩模，将纹理引入多晶硅层的表面。然后清洁多晶硅层的表面，并在纹理多晶硅表面上提供电容器电介质和上电容器电极。

2. 发明授权

US6030867A Method of fabricating a Fin/HSG DRAM cell capacitor 失效
标题翻译：制造Fin / HSG DRAM单元电容器的方法
公开(公告)号：US6030867A
公开(公告)日：2000-02-29
申请号：US975708
申请日：1997-11-21
申请人： Sun-Chieh Chien , Jason Jenq , Der-Yuan Wu , Chia-Wen Liang
发明人： Sun-Chieh Chien , Jason Jenq , Der-Yuan Wu , Chia-Wen Liang
IPC分类号： H01L21/02 , H01L21/60 , H01L21/768 , H01L21/8242
CPC分类号： H01L24/11 , H01L27/10852 , H01L28/84 , H01L21/76895 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： The DRAM cell is formed by covering the cell's transfer FET with a conformal insulating layer. A self aligned contact etch removes a portion of the conformal insulating layer from above a first source/drain region of the FET and then a first polysilicon layer is deposited over the device. Etching defines a polysilicon pad from the first polysilicon layer with edges of the polysilicon pad disposed over the gate electrode and an adjacent wiring line. A thick, planarized second insulating layer is provided over the device, filling the volume defined by the locally cupped surface of the polysilicon pad. Etching is performed to remove a portion of the planarized insulating layer using the pad polysilicon layer as an etch stop for the process. A second, thick polysilicon layer is next provided to fill the cavity and the layer is patterned to laterally define the lower capacitor electrode. Hemispherical grained silicon (HSG-Si) is deposited on the surface of the patterned polysilicon layer and an etch back process is used to transfer the topology of the HSG-Si layer to the underlying polysilicon. Further processing provides a capacitor dielectric and an upper electrode.
摘要翻译：通过用保形绝缘层覆盖电池的转移FET来形成DRAM单元。自对准接触蚀刻从FET的第一源极/漏极区上方去除保形绝缘层的一部分，然后在器件上沉积第一多晶硅层。蚀刻定义了来自第一多晶硅层的多晶硅焊盘，其中多晶硅焊盘的边缘设置在栅电极和相邻布线之上。在该器件上方提供厚的平坦化的第二绝缘层，填充由多晶硅垫的局部杯形表面限定的体积。使用焊盘多晶硅层作为该工艺的蚀刻停止来执行蚀刻以去除平坦化绝缘层的一部分。接下来提供第二厚的多晶硅层以填充空腔，并且对该层进行图案化以横向限定下部电容器电极。半球形晶粒硅（HSG-Si）沉积在图案化的多晶硅层的表面上，并且使用回蚀工艺将HSG-Si层的拓扑转移到下面的多晶硅。进一步的处理提供电容器电介质和上电极。

3. 发明授权

US5874335A Method of fabricating DRAM capacitors 失效
标题翻译：制造DRAM电容器的方法
公开(公告)号：US5874335A
公开(公告)日：1999-02-23
申请号：US27523
申请日：1998-02-23
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90
摘要： A method for fabricating a semiconductor device is provided comprising forming a dual silicon nitride spacer to be an etching step layer during a self-aligned contact etching step. The invention discloses a bottom electrode with a tri-forked structure and a hemispherical grain layer of a capacitor, therefore the capacitor has a larger surface area. So the capacitor made by the invention has a high capacitance even though the planar surface size is reduced continually.
摘要翻译：提供了一种制造半导体器件的方法，包括在自对准接触蚀刻步骤期间形成作为蚀刻步骤层的双重氮化硅间隔物。本发明公开了一种具有三叉结构的底电极和电容器的半球形晶粒层，因此电容器具有较大的表面积。因此，即使平面表面尺寸连续减小，本发明制成的电容器具有高电容。

4. 发明授权

US5981334A Method of fabricating DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US5981334A
公开(公告)日：1999-11-09
申请号：US965326
申请日：1997-11-06
申请人： Sun-Chieh Chien , Jason Jenq , C. C. Hsue
发明人： Sun-Chieh Chien , Jason Jenq , C. C. Hsue
IPC分类号： H01L21/02 , H01L21/70 , H01L21/00
CPC分类号： H01L28/82 , H01L28/84 , H01L28/91
摘要： A method for fabricating DRAM capacitor which includes forming a transistor having a source/drain regions and a gate electrode above a silicon substrate; then, forming sequentially a stack of layers including a first insulating layer, a second insulating layer, a third insulating layer and a hard mask layer over the transistor; subsequently, patterning and etching the hard mask layer. Thereafter, an oxide layer is formed over the hard mask layer, and then portions of the layers are etched to form a capacitor region over the oxide layer and a contact opening exposing a portion of the source/drain region. In the subsequent step, a conducting layer is formed over the oxide layer, the hard mask layer, the sidewalls of the contact opening and the exposed portion of the source/drain region. Next, a polishing method is used to remove the conducting layer above the oxide layer, and then the oxide layer is removed to form a lower electrode. A dielectric layer is then formed over the lower electrode, and finally an upper electrode layer is formed over the dielectric layer.
摘要翻译：一种用于制造DRAM电容器的方法，其包括在硅衬底上形成具有源极/漏极区域和栅极电极的晶体管; 然后在晶体管上依次形成包括第一绝缘层，第二绝缘层，第三绝缘层和硬掩模层的层叠层; 随后，对硬掩模层进行图案化和蚀刻。此后，在硬掩模层之上形成氧化物层，然后蚀刻这些层的一部分以在氧化物层上形成电容器区域，以及暴露源极/漏极区域的一部分的接触开口。在随后的步骤中，在氧化物层，硬掩模层，接触开口的侧壁和源极/漏极区域的暴露部分之上形成导电层。接下来，使用抛光方法去除氧化物层上方的导电层，然后除去氧化物层以形成下电极。然后在下电极上形成电介质层，最后在电介质层上形成上电极层。

5. 发明授权

US5960280A Method of fabricating a fin/cavity capacitor structure for DRAM cell 失效
标题翻译：制造用于DRAM单元的鳍/腔电容器结构的方法
公开(公告)号：US5960280A
公开(公告)日：1999-09-28
申请号：US975489
申请日：1997-11-21
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84
摘要： A DRAM is formed by providing a transfer FET, providing an elevated structure over and adjacent to the transfer FET and then forming a cavity above one of the source/drain regions of the transfer FET. The cavity is filled with a conductor to define in part a lower electrode of a charge storage capacitor. Portions of the cavity are then removed to expose additional charge storage surfaces for the lower electrode of the charge storage capacitor. The elevated structure includes a thick, planarized insulating layer provided over the transfer FET. A cavity is formed by providing an etching mask over the thick, planarized insulating layer with an opening positioned over the first source/drain. Etching is performed to remove a portion of the second insulating layer. A thick polysilicon layer is provided to fill the cavity and then the second, thick polysilicon layer is patterned to laterally define the lower capacitor electrode, preferably leaving portions of the second polysilicon layer extending above the stepped opening and onto surrounding portions of the second insulating layer. The second insulating layer is then removed to expose additional surfaces of the lower capacitor electrode for charge storage. Processing continues to provide a capacitor dielectric layer, an upper capacitor electrode and a bit line contact to complete the DRAM.
摘要翻译：通过提供转移FET来形成DRAM，在转移FET上方并且靠近转移FET，然后在转移FET的源极/漏极区之一上形成空腔。空腔填充有导体，部分地限定电荷存储电容器的下电极。然后去除腔的部分以暴露电荷存储电容器的下电极的附加电荷存储表面。升高的结构包括设置在转移FET上的厚的平坦化绝缘层。通过在厚的平坦化绝缘层上设置蚀刻掩模形成空腔，其中开口位于第一源极/漏极之上。执行蚀刻以去除第二绝缘层的一部分。提供厚多晶硅层以填充空腔，然后将第二厚多晶硅层图案化以横向限定下电容器电极，优选地使第二多晶硅层的部分在阶梯开口上方延伸到第二绝缘层的周围部分。然后去除第二绝缘层以露出用于电荷存储的下部电容器电极的附加表面。处理继续提供电容器介电层，上电容器电极和位线接触来完成DRAM。

6. 发明授权

US06153465A Method of fabricating a capacitor of dynamic random access memory 失效
标题翻译：制造动态随机存取存储器电容器的方法
公开(公告)号：US06153465A
公开(公告)日：2000-11-28
申请号：US8863
申请日：1998-01-20
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/84 , H01L27/10852
摘要： A method of fabricating a capacitor of a dynamic random access memory is provided. A substrate is first provided, wherein a first dielectric layer is formed on the substrate, and a via is formed through the first dielectric layer to expose one of source/drain regions. A conductive material is formed on the first dielectric layer so that the conductive material is filled in the via to contact with the one of the source/drain regions. The conductive material is patterned to form a first conductive layer. A hemispherical polysilicon grain layer is formed at least on the first conductive layer. The hemispherical polysilicon grain layer is etched back so that the first conductive layer and the hemispherical polysilicon grain layer together form a lower electrode. A second dielectric layer is formed on the lower electrode. A second conductive layer is formed on the second dielectric layer to be an upper electrode.
摘要翻译：提供一种制造动态随机存取存储器的电容器的方法。首先提供衬底，其中在衬底上形成第一电介质层，并且通过第一介电层形成通孔以暴露源/漏区之一。导电材料形成在第一电介质层上，使得导电材料填充在通孔中以与源/漏区之一接触。将导电材料图案化以形成第一导电层。至少在第一导电层上形成半球状多晶硅晶粒层。半球形多晶硅晶粒层被回蚀刻，使得第一导电层和半球形多晶硅晶粒层一起形成下电极。在下电极上形成第二电介质层。在第二电介质层上形成第二导电层作为上电极。

7. 发明授权

US6121085A Method of fabricating contact openings for dynamic random-access memory 失效
标题翻译：制造用于动态随机存取存储器的接触孔的方法
公开(公告)号：US6121085A
公开(公告)日：2000-09-19
申请号：US9508
申请日：1998-01-20
申请人： Chia-Wen Liang , Sun-Chieh Chien , Der-Yuan Wu , Jason Jenq
发明人： Chia-Wen Liang , Sun-Chieh Chien , Der-Yuan Wu , Jason Jenq
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852
摘要： A method of making contact openings for memory cell units of DRAM IC devices is disclosed. The contact opening is used to connect the cell transistor source/drain terminal to the storage capacitor electrode located substantially above. The method includes the step of first patterning the initial opening in a shielding layer for the contact opening. The diameter of the initial opening is then reduced by the formation of sidewall spacers in initial opening. The initial opening in the shielding layer is then used to implement the etching for the formation of the contact opening. Due to reduced size of the contact opening, short-circuiting situations arising between the via formed in the contact opening and the bit lines next to the via as a result of misalignment in the process of fabrication can be reduced, thereby improving the device fabrication yield rates.
摘要翻译：公开了一种制造DRAM IC器件的存储单元的接触开口的方法。接触开口用于将单元晶体管源极/漏极端子连接到大致位于上方的存储电容器电极。该方法包括首先在接触开口的屏蔽层中构图初始开口的步骤。然后通过在初始开口中形成侧壁间隔来减小初始开口的直径。然后使用屏蔽层中的初始开口来实现用于形成接触开口的蚀刻。由于接触开口的尺寸减小，可以减少在制造工艺中由于在接触开口中形成的通孔与通孔旁边的位线之间产生的短路情况，从而提高器件的制造成品率价格。

8. 发明授权

US6080619A Method for manufacturing DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US6080619A
公开(公告)日：2000-06-27
申请号：US85903
申请日：1998-05-27
申请人： Sun-Chieh Chien , King-Lung Wu , Chuan-Fu Wang , Jason Jenq
发明人： Sun-Chieh Chien , King-Lung Wu , Chuan-Fu Wang , Jason Jenq
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90
摘要： A method for manufacturing a DRAM capacitor is provided to form a lower electrode with a cylindrical profile by using a first stage and a second stage. The stages provide different etching rates in various situations. The invention uses the stages to allow the part of the second polysilicon layer between the capacitors to be completely etched and prevent the other part of the second polysilicon layer serving as a lower electrode from over-etching. The invention provides an easier process of forming a cylindrical capacitor with a larger surface.
摘要翻译：提供一种用于制造DRAM电容器的方法，以通过使用第一级和第二级形成具有圆柱形轮廓的下电极。这些阶段在各种情况下提供不同的蚀刻速率。本发明使用这些阶段来允许电容器之间的第二多晶硅层的一部分被完全蚀刻，并且防止用作下部电极的第二多晶硅层的另一部分过度蚀刻。本发明提供了形成具有更大表面的圆柱形电容器的更容易的工艺。

9. 发明授权

US5924007A Method for improving the planarization of inter-poly dielectric 失效
标题翻译：改进多晶硅电介质平面化的方法
公开(公告)号：US5924007A
公开(公告)日：1999-07-13
申请号：US910999
申请日：1997-08-14
申请人： Chia-Wen Liang , Jason Jenq , Chuan-Fu Wang , Sun-Chieh Chien
发明人： Chia-Wen Liang , Jason Jenq , Chuan-Fu Wang , Sun-Chieh Chien
IPC分类号： H01L21/321 , H01L21/469
CPC分类号： H01L21/321
摘要： A method of improving the planarization of inter-poly dielectric layers. On a semiconductor device on which a poly-silicon layer is formed, by using atmosphere chemical vapor deposition, an undoped inter-poly dielectric layer is formed. A doped inter-poly dielectric layer is formed on the undoped inter-poly dielectric layer. Under a high temperature, reflow and etching back operations are performed for the doped inter-poly dielectric layer. Before a second poly-silicon layer is formed, a rapid thermal process is performed.
摘要翻译：一种改善多晶硅介电层平坦化的方法。在形成多晶硅层的半导体器件上，通过使用气氛化学气相沉积，形成未掺杂的多晶硅间介质层。在未掺杂的多晶硅间介质层上形成掺杂的多晶硅介电层。在高温下，对掺杂的多晶硅介电层进行回流和回蚀作业。在形成第二多晶硅层之前，进行快速热处理。

10. 发明授权

US5872055A Method for fabricating polysilicon conducting wires 失效
标题翻译：制造多晶硅导线的方法
公开(公告)号：US5872055A
公开(公告)日：1999-02-16
申请号：US768971
申请日：1996-12-18
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/3213 , H01L21/768 , H01L21/306 , H01L21/311
CPC分类号： H01L21/32139 , H01L21/32134 , H01L21/76885
摘要： A manufacturing method of fabricating a polysilicon conductive wire suitable for an integrated circuit and which can avoid pattern transfer errors caused by reflection of ultraviolet light during photolithographic processing and that results in constriction in width or the bottlenecking effect in part of the conductive wore. A polysilicon layer is formed above a semiconductor substrate having a preformed device. A cap insulting layer is formed above the polysilicon layer. A micro-roughness structure is formed on the surface of the cap insulating layer. A photoresist layer is coated over the micro-roughened surface of the cap insulating layer. A pattern is transferred onto the photoresist layer by selective light exposure followed by the removal of unexposed photoresist. Then the cap insulating layer and the polysilicon layer are etched in sequence in regions not covered by photoresist. The residual photoresist is then removed to leave behind a polysilicon conductive wire.
摘要翻译：一种制造适用于集成电路的多晶硅导线的制造方法，其可以避免在光刻处理期间由紫外光的反射引起的图案转移误差，并且导致部分导电磨损的宽度缩窄或瓶颈效应。在具有预成型器件的半导体衬底之上形成多晶硅层。在多晶硅层上方形成帽绝缘层。在帽绝缘层的表面上形成微粗糙结构。将光致抗蚀剂层涂覆在帽绝缘层的微粗糙表面上。通过选择性曝光然后去除未曝光的光致抗蚀剂将图案转印到光致抗蚀剂层上。然后在未被光致抗蚀剂覆盖的区域中依次蚀刻帽绝缘层和多晶硅层。然后去除剩余光致抗蚀剂留下多晶硅导电线。

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