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1. 发明授权

US08638632B2 Access line management in a memory device 有权
标题翻译：存储设备中的接入线管理
公开(公告)号：US08638632B2
公开(公告)日：2014-01-28
申请号：US12888765
申请日：2010-09-23
申请人： Benjamin Louie , Ali Mohammadzadeh , Aaron Yip
发明人： Benjamin Louie , Ali Mohammadzadeh , Aaron Yip
IPC分类号： G11C5/14
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
摘要： Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
摘要翻译：公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。

2. 发明申请

US20120075934A1 ACCESS LINE MANAGEMENT IN A MEMORY DEVICE 有权
标题翻译：存储设备中的线路管理
公开(公告)号：US20120075934A1
公开(公告)日：2012-03-29
申请号：US12888765
申请日：2010-09-23
申请人： Benjamin Louie , Ali Mohammadzadeh , Aaron Yip
发明人： Benjamin Louie , Ali Mohammadzadeh , Aaron Yip
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
摘要： Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
摘要翻译：公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。

3. 发明申请

US20100142280A1 PROGRAMMING MEMORY DEVICES 有权
标题翻译：编程存储器件
公开(公告)号：US20100142280A1
公开(公告)日：2010-06-10
申请号：US12703901
申请日：2010-02-11
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
摘要翻译：通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为目标存储单元未编程。在制造存储器件之后，可以选择初始编程电压和阶跃电压。

4. 发明申请

US20080074933A1 RANDOM CACHE READ 有权
标题翻译：随机缓存阅读
公开(公告)号：US20080074933A1
公开(公告)日：2008-03-27
申请号：US11515629
申请日：2006-09-05
申请人： Benjamin Louie , Yunqiu Wan , Aaron Yip , Jin-Man Han
发明人： Benjamin Louie , Yunqiu Wan , Aaron Yip , Jin-Man Han
IPC分类号： G11C7/10
CPC分类号： G11C7/1042 , G11C7/1051 , G11C16/26 , G11C2207/2245
摘要： A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.
摘要翻译：描述了利用高速缓存读取操作模式的非易失性存储器，其中由读出放大器从存储器阵列读取/感测存储器的下一页，同时从存储器I / O缓冲器，其中下一页是用户选择的。这种随机高速缓存读取模式允许具有随机页面读取功能的存储器，其中要读取的下一页数据的地址是用户可选择的，这受益于由于并发数据而导致的高速缓存读取操作模式的低等待时间感测和数据I / O。

5. 发明授权

US07345924B2 Programming memory devices 有权
标题翻译：编程存储器件
公开(公告)号：US07345924B2
公开(公告)日：2008-03-18
申请号：US11546171
申请日：2006-10-11
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
摘要翻译：通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为目标存储单元未编程。在制造存储器件之后，可以选择初始编程电压和阶跃电压。

6. 发明授权

US07336537B2 Handling defective memory blocks of NAND memory devices 有权
公开(公告)号：US07336537B2
公开(公告)日：2008-02-26
申请号：US11487857
申请日：2006-07-17
申请人： Benjamin Louie , Aaron Yip
发明人： Benjamin Louie , Aaron Yip
IPC分类号： G11C16/06
CPC分类号： G11C29/832 , G11C16/04 , G11C16/0483 , G11C29/26 , G11C29/789 , G11C29/82 , G11C2029/4402
摘要： Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively preventing testing of the respective memory block coupled thereto when that memory block is a known defective block. A non-volatile latch may also be coupled to each of the memory blocks for permanently preventing access, during normal operation of the memory device, to the respective memory block coupled thereto when that memory block is a known defective block.

7. 发明申请

US20050286337A1 Handling defective memory blocks of NAND memory devices 有权
标题翻译：处理NAND存储器件的缺陷存储块
公开(公告)号：US20050286337A1
公开(公告)日：2005-12-29
申请号：US10876878
申请日：2004-06-25
申请人： Benjamin Louie , Aaron Yip
发明人： Benjamin Louie , Aaron Yip
IPC分类号： G11C8/02 , G11C16/04 , G11C29/00 , G11C29/26
CPC分类号： G11C29/832 , G11C16/04 , G11C16/0483 , G11C29/26 , G11C29/789 , G11C29/82 , G11C2029/4402
摘要： Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively preventing testing of the respective memory block coupled thereto when that memory block is a known defective block. A non-volatile latch may also be coupled to each of the memory blocks for permanently preventing access, during normal operation of the memory device, to the respective memory block coupled thereto when that memory block is a known defective block.
摘要翻译：提供了装置和方法。 NAND存储器件具有包括多个存储器块的存储器阵列和耦合到每个存储器块的易失性锁存器，用于当该存储器块是已知缺陷块时选择性地防止与其耦合的存储器块的测试。非易失性锁存器还可以耦合到每个存储器块，以在存储器装置的正常操作期间永久地防止当该存储器块是已知缺陷块时与其耦合的相应存储器块的存取。

8. 发明授权

US08174889B2 Programming memory devices 有权
标题翻译：编程存储器件
公开(公告)号：US08174889B2
公开(公告)日：2012-05-08
申请号：US12703901
申请日：2010-02-11
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
摘要翻译：通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为目标存储单元未编程。在制造存储器件之后，可以选择初始编程电压和阶跃电压。

9. 发明申请

US20090154247A1 PROGRAMMING MEMORY DEVICES 失效
标题翻译：编程存储器件
公开(公告)号：US20090154247A1
公开(公告)日：2009-06-18
申请号：US12370810
申请日：2009-02-13
申请人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung H. Nguyen , Benjamin Louie , Hagop A. Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
摘要翻译：通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为目标存储单元未编程。在制造存储器件之后，可以选择初始编程电压和阶跃电压。

10. 发明授权

US07369447B2 Random cache read 有权
标题翻译：随机缓存读取
公开(公告)号：US07369447B2
公开(公告)日：2008-05-06
申请号：US11515629
申请日：2006-09-05
申请人： Benjamin Louie , Yunqiu Wan , Aaron Yip , Jin-Man Han
发明人： Benjamin Louie , Yunqiu Wan , Aaron Yip , Jin-Man Han
IPC分类号： G11C7/00
CPC分类号： G11C7/1042 , G11C7/1051 , G11C16/26 , G11C2207/2245
摘要： A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.
摘要翻译：描述了利用高速缓存读取操作模式的非易失性存储器，其中由读出放大器从存储器阵列读取/感测存储器的下一页，同时从存储器I / O缓冲器，其中下一页是用户选择的。这种随机高速缓存读取模式允许具有随机页面读取功能的存储器，其中要读取的下一页数据的地址是用户可选择的，这受益于由于并发数据而导致的高速缓存读取操作模式的低等待时间感测和数据I / O。

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