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1. 发明授权

US08638632B2 Access line management in a memory device 有权
标题翻译：存储设备中的接入线管理
公开(公告)号：US08638632B2
公开(公告)日：2014-01-28
申请号：US12888765
申请日：2010-09-23
申请人： Benjamin Louie , Ali Mohammadzadeh , Aaron Yip
发明人： Benjamin Louie , Ali Mohammadzadeh , Aaron Yip
IPC分类号： G11C5/14
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
摘要： Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
摘要翻译：公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。

2. 发明申请

US20120075934A1 ACCESS LINE MANAGEMENT IN A MEMORY DEVICE 有权
标题翻译：存储设备中的线路管理
公开(公告)号：US20120075934A1
公开(公告)日：2012-03-29
申请号：US12888765
申请日：2010-09-23
申请人： Benjamin Louie , Ali Mohammadzadeh , Aaron Yip
发明人： Benjamin Louie , Ali Mohammadzadeh , Aaron Yip
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
摘要： Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
摘要翻译：公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。

3. 发明申请

US20160093379A1 NAND MEMORY ADDRESSING 有权
标题翻译： NAND存储器寻址
公开(公告)号：US20160093379A1
公开(公告)日：2016-03-31
申请号：US14498084
申请日：2014-09-26
申请人： Umberto Siciliani , Tommaso Vali , Terry Grunzke , Ali Mohammadzadeh
发明人： Umberto Siciliani , Tommaso Vali , Terry Grunzke , Ali Mohammadzadeh
IPC分类号： G11C16/08
CPC分类号： G11C16/08 , G06F12/06 , G06F2212/2022 , G11C5/066 , G11C7/1045 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C27/02 , G11C2211/5641
摘要： Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).
摘要翻译：描述在NAND存储器中执行寻址的技术。可以识别在存储器控制器或NAND存储器中支持的用于寻址NAND存储器中的各个存储器单元的定义数量的地址周期。可以选择要定义的操作地址周期数，以便寻址NAND存储器中的各个存储器单元。可以将存储器控制器或NAND存储器配置为以所选择的地址周期数进行操作，其中NAND存储器中的各个存储器单元使用多管芯选择（MDS）可唯一寻址。

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