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1. 发明授权

US07838862B2 Phase random access memory with high density 有权
标题翻译：高密度相位随机存取存储器
公开(公告)号：US07838862B2
公开(公告)日：2010-11-23
申请号：US11177115
申请日：2005-07-08
申请人： Hyung-Rok Oh , Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Hyung-Rok Oh , Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： H01L47/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/122 , H01L45/144
摘要： A phase random access memory including a plurality of access transistors, each access transistor including a drain region and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.
摘要翻译：一种包括多个存取晶体管的相位随机存取存储器，每个存取晶体管包括漏区和由多个存取晶体管共享的相变膜。相变膜通过第一电极连接到位线，并通过多个第二电极中的至少一个连接到每个相应的漏极区域。

2. 发明授权

US07511993B2 Phase change memory device and related programming method 有权
标题翻译：相变存储器件及相关编程方法
公开(公告)号：US07511993B2
公开(公告)日：2009-03-31
申请号：US11724268
申请日：2007-03-15
申请人： Byung-Gil Choi , Du-Eung Kim , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device comprises a memory cell array and a write driver circuit. The memory cell array comprises a plurality of memory cells, and the write driver circuit comprises a set current driver and a reset current driver. The set current driver is adapted to provide a set current to a selected memory cell among the plurality of memory cells and the reset current driver is adapted to provide a reset current to a selected memory cell among the plurality of memory cells.
摘要翻译：相变存储器件包括存储单元阵列和写入驱动器电路。存储单元阵列包括多个存储单元，并且写驱动器电路包括设定电流驱动器和复位电流驱动器。所设置的电流驱动器适于向所述多个存储器单元中的所选择的存储单元提供设定电流，并且所述复位电流驱动器适于向所述多个存储器单元中的所选存储单元提供复位电流。

3. 发明申请

US20070133271A1 Phase-changeable memory device and read method thereof 有权
标题翻译：相变存储器件及其读取方法
公开(公告)号：US20070133271A1
公开(公告)日：2007-06-14
申请号：US11605212
申请日：2006-11-29
申请人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.
摘要翻译：公开了一种可变相存储器件和读取数据的相关方法。存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。每个存储单元包括相位可变材料和连接到位线的二极管。高压电路从电源提供高电压。预充电电路将位线充电至电源电压后，将位线升高至高电压。偏置电路通过高电压向位线提供读取电流。读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

4. 发明申请

US20070133269A1 Non-volatile memory devices and systems including phase-change one-time-programmable (OTP) memory cells and related methods 有权
标题翻译：包括相变一次可编程（OTP）存储单元和相关方法的非易失性存储器件和系统
公开(公告)号：US20070133269A1
公开(公告)日：2007-06-14
申请号：US11488010
申请日：2006-07-18
申请人： Kwang-Jin Lee , Woo-Yeong Cho , Du-Eung Kim , Beak-Hyung Cho
发明人： Kwang-Jin Lee , Woo-Yeong Cho , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0059 , G11C17/16 , G11C17/165
摘要： In one aspect, a non-volatile memory includes a phase-change memory cell array which includes a plurality of normal phase-change memory cells and a plurality of pseudo one-time-programmable (OTP) phase-change memory cells, a write driver which writes data into the normal and pseudo OTP phase-change memory cells of the phase-change memory cell array, and an OTP controller which selectively disables the write driver.
摘要翻译：一方面，非易失性存储器包括相变存储单元阵列，其包括多个正常相变存储器单元和多个伪一次可编程（OTP）相变存储器单元，写入驱动器其将数据写入相变存储单元阵列的正常和伪OTP相变存储单元，以及选择性地禁用写入驱动器的OTP控制器。

5. 发明申请

US20050247922A1 Phase random access memory with high density 有权
标题翻译：高密度相位随机存取存储器
公开(公告)号：US20050247922A1
公开(公告)日：2005-11-10
申请号：US11177115
申请日：2005-07-08
申请人： Hyung-Rok Oh , Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Hyung-Rok Oh , Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C13/00 , G11B7/24 , G11C11/56 , G11C16/02 , H01L27/10 , H01L27/105 , H01L27/24 , H01L29/76 , H01L45/00 , H01L47/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/122 , H01L45/144
摘要： A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.
摘要翻译：一种包括多个存取晶体管的相位随机存取存储器，每个存取晶体管包括漏极区域，以及由多个存取晶体管共享的可相位改变的薄膜。相变膜通过第一电极连接到位线，并通过多个第二电极中的至少一个连接到每个相应的漏极区域。

6. 发明申请

US20110242886A1 Apparatus and Systems Using Phase Change Memories 有权
标题翻译：使用相变记忆的装置和系统
公开(公告)号：US20110242886A1
公开(公告)日：2011-10-06
申请号：US13091238
申请日：2011-04-21
申请人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/21
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092
摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.
摘要翻译：提供了使用相变存储器件的装置和系统。相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。每个顺序复位脉冲被输出到多个复位线中相应的一个。多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

7. 发明授权

US07391644B2 Phase-changeable memory device and read method thereof 有权
标题翻译：相变存储器件及其读取方法
公开(公告)号：US07391644B2
公开(公告)日：2008-06-24
申请号：US11605212
申请日：2006-11-29
申请人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.
摘要翻译：公开了一种可变相存储器件和读取数据的相关方法。存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。每个存储单元包括相位可变材料和连接到位线的二极管。高压电路从电源提供高电压。预充电电路将位线充电至电源电压后，将位线升高至高电压。偏置电路通过高电压向位线提供读取电流。读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

8. 发明申请

US20080137402A1 APPARATUS AND SYSTEMS USING PHASE CHANGE MEMORIES 有权
标题翻译：使用相变记忆的装置和系统
公开(公告)号：US20080137402A1
公开(公告)日：2008-06-12
申请号：US11949342
申请日：2007-12-03
申请人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092
摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.
摘要翻译：提供了使用相变存储器件的装置和系统。相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。每个顺序复位脉冲被输出到多个复位线中相应的一个。多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

9. 发明申请

US20070230240A1 Phase change memory device and related programming method 有权
标题翻译：相变存储器件及相关编程方法
公开(公告)号：US20070230240A1
公开(公告)日：2007-10-04
申请号：US11724268
申请日：2007-03-15
申请人： Byung-Gil Choi , Du-Eung Kim , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device comprises a memory cell array and a write driver circuit. The memory cell array comprises a plurality of memory cells, and the write driver circuit comprises a set current driver and a reset current driver. The set current driver is adapted to provide a set current to a selected memory cell among the plurality of memory cells and the reset current driver is adapted to provide a reset current to a selected memory cell among the plurality of memory cells.
摘要翻译：相变存储器件包括存储单元阵列和写入驱动器电路。存储单元阵列包括多个存储单元，并且写驱动器电路包括设定电流驱动器和复位电流驱动器。所设置的电流驱动器适于向所述多个存储器单元中的所选择的存储单元提供设定电流，并且所述复位电流驱动器适于向所述多个存储器单元中的所选存储单元提供复位电流。

10. 发明授权

US07994493B2 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US07994493B2
公开(公告)日：2011-08-09
申请号：US12196137
申请日：2008-08-21
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.
摘要翻译：相变存储器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线。字线可以具有不同于第一导电类型和基本上平坦的顶表面的第二导电类型。第一和第二半导体图案可以顺序地堆叠在每个字线上，并且可以提供绝缘层以填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体图案之间的间隙区域。多个相变材料图案可以二维排列在绝缘层上并电连接到第二半导体图案。

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