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1. 发明申请

US20120146104A1 STRUCTURE AND LAYOUT OF A FET PRIME CELL 有权
标题翻译： FET母细胞的结构和布局
公开(公告)号：US20120146104A1
公开(公告)日：2012-06-14
申请号：US13398408
申请日：2012-02-16
申请人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
发明人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
IPC分类号： H01L29/06
CPC分类号： H01L29/78 , H01L23/4824 , H01L29/1087
摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
摘要翻译：制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触，漏极和栅极以及基板。

2. 发明授权

US08829572B2 Structure and layout of a FET prime cell 有权
标题翻译： FET素电池的结构和布局
公开(公告)号：US08829572B2
公开(公告)日：2014-09-09
申请号：US13398408
申请日：2012-02-16
申请人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
发明人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
IPC分类号： H01L29/66 , H01L27/088 , H01L21/70 , H01L23/552
CPC分类号： H01L29/78 , H01L23/4824 , H01L29/1087
摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
摘要翻译：制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触，漏极和栅极以及基板。

3. 发明授权

US08187930B2 Structure and layout of a FET prime cell 有权
标题翻译： FET素电池的结构和布局
公开(公告)号：US08187930B2
公开(公告)日：2012-05-29
申请号：US11923686
申请日：2007-10-25
申请人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
发明人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
IPC分类号： H01L21/337
CPC分类号： H01L29/78 , H01L23/4824 , H01L29/1087
摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
摘要翻译：制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触，漏极和栅极以及基板。

4. 发明授权

US08916440B2 Semiconductor structures and methods of manufacture 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US08916440B2
公开(公告)日：2014-12-23
申请号：US13566404
申请日：2012-08-03
申请人： William F. Clark, Jr. , Qizhi Liu , John J. Pekarik , Yun Shi , Yanli Zhang
发明人： William F. Clark, Jr. , Qizhi Liu , John J. Pekarik , Yun Shi , Yanli Zhang
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L21/336 , H01L29/40
CPC分类号： H01L27/0623 , H01L21/823418 , H01L21/8249 , H01L27/088 , H01L27/0922 , H01L29/04 , H01L29/161 , H01L29/402 , H01L29/45 , H01L29/66659 , H01L29/7302 , H01L29/735 , H01L29/78 , H01L29/7817 , H01L29/7835
摘要： Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.
摘要翻译：本文公开了半导体结构和制造方法。具体地，本文公开了制造高压金属氧化物半导体场效应晶体管和各种结构的方法。一种方法包括在FET区域的衬底上形成场效应晶体管（FET），在HVFET区域中的过掺杂掺杂扩散（LDD）漏极上的介质堆叠上形成高电压FET（HVFET），以及在NPN区域的基板上形成NPN。

5. 发明申请

US20140035064A1 SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE 有权
标题翻译：半导体结构和制造方法
公开(公告)号：US20140035064A1
公开(公告)日：2014-02-06
申请号：US13566404
申请日：2012-08-03
申请人： William F. CLARK, JR. , Qizhi LIU , John J. Pekarik , Yun SHI , Yanli ZHANG
发明人： William F. CLARK, JR. , Qizhi LIU , John J. Pekarik , Yun SHI , Yanli ZHANG
IPC分类号： H01L21/8249 , H01L27/06
CPC分类号： H01L27/0623 , H01L21/823418 , H01L21/8249 , H01L27/088 , H01L27/0922 , H01L29/04 , H01L29/161 , H01L29/402 , H01L29/45 , H01L29/66659 , H01L29/7302 , H01L29/735 , H01L29/78 , H01L29/7817 , H01L29/7835
摘要： Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.
摘要翻译：本文公开了半导体结构和制造方法。具体地，本文公开了制造高压金属氧化物半导体场效应晶体管和各种结构的方法。一种方法包括在FET区域的衬底上形成场效应晶体管（FET），在HVFET区域中的过掺杂掺杂扩散（LDD）漏极上的介质堆叠上形成高电压FET（HVFET），以及在NPN区域的基板上形成NPN。

6. 发明授权

US08610174B2 Bipolar transistor with a raised collector pedestal for reduced capacitance 有权
标题翻译：双极晶体管带有集电极基座，用于降低电容
公开(公告)号：US08610174B2
公开(公告)日：2013-12-17
申请号：US13307412
申请日：2011-11-30
申请人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L31/109
CPC分类号： H01L29/66234 , H01L29/0826 , H01L29/66287 , H01L29/732 , H01L29/7371
摘要： Disclosed is a transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.
摘要翻译：公开了具有降低的集电极基座的晶体管，用于减小基极 - 集电极结电容。凸起的收集器基座位于基板的顶表面上，垂直延伸穿过绝缘层（未掺杂或低掺杂）在衬底内的子集电极区域上方排列，收集区域。本征基层在凸起的收集器基座和介电层之上。外在基层在本征基层之上。因此，外部基极层和副集电极区域之间的空间增加。该增加的空间由电介质材料填充，并且本征基极层和次集电极区域之间的电连接由相对窄的未掺杂或低掺杂的升高的集电极基座提供。因此，集电极结电容减小，因此最大振荡频率增加。

7. 发明申请

US20110291171A1 VARACTOR 审中-公开
标题翻译：变量
公开(公告)号：US20110291171A1
公开(公告)日：2011-12-01
申请号：US13050043
申请日：2011-03-17
申请人： John J. Pekarik , William F. Clark, JR. , Robert J. Gauthier, JR. , Yun Shi , Yanli Zhang
发明人： John J. Pekarik , William F. Clark, JR. , Robert J. Gauthier, JR. , Yun Shi , Yanli Zhang
IPC分类号： H01L29/92 , H01L21/8234
CPC分类号： H01L29/93 , H01L27/0808 , H01L27/0811 , H01L29/78
摘要： A variable capacitance device including a plurality of FETs, the sources and drains of each FET being coupled to a first terminal, the gates of each FET being coupled to a second terminal, the capacitance of said device between said first and second terminals varying as a function of the voltage across said terminals, the device further including a biasing providing a respective backgate bias voltage to each the FETs setting a respective gate threshold voltage thereof. The aggregate V-C characteristic can be tuned as desired, either at design time or dynamically. The greater the number of FETs forming the varactor, the greater the number of possible Vt values that can be individually set, so that arbitrary V-C characteristics can be more closely approximated.
摘要翻译：一种包括多个FET的可变电容器件，每个FET的源极和漏极耦合到第一端子，每个FET的栅极耦合到第二端子，所述器件在所述第一和第二端子之间的电容变化为所述器件还包括偏置电路，为每个FET提供相应的背栅极偏置电压，从而设置其相应的栅极阈值电压。可以在设计时或动态地根据需要调整总体V-C特性。形成变容二极管的FET数量越多，可以单独设置的可能的Vt值的数量就越多，从而可以更接近任意的V-C特性。

8. 发明授权

US07382029B2 Method and apparatus for improving integrated circuit device performance using hybrid crystal orientations 有权
标题翻译：使用混合晶体取向提高集成电路器件性能的方法和装置
公开(公告)号：US07382029B2
公开(公告)日：2008-06-03
申请号：US11161337
申请日：2005-07-29
申请人： John J. Pekarik , Xudong Wang
发明人： John J. Pekarik , Xudong Wang
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L21/823807 , H01L29/045
摘要： A method for implementing a desired offset in device characteristics of an integrated circuit includes forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation, and forming a second device of the first conductivity type on a second portion of the substrate having a second crystal lattice orientation. The carrier mobility of the first device formed on the first crystal lattice orientation is greater than the carrier mobility of the second device formed on the second crystal lattice orientation.
摘要翻译：在集成电路的器件特性中实现期望偏移的方法包括在具有第一晶格取向的衬底的第一部分上形成第一导电类型的第一器件，以及在第一导电类型的第一部分上形成第一导电类型的第二器件所述基板的第二部分具有第二晶格取向。形成在第一晶格取向上的第一器件的载流子迁移率大于在第二晶格取向上形成的第二器件的载流子迁移率。

9. 发明授权

US08921190B2 Field effect transistor and method of manufacture 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US08921190B2
公开(公告)日：2014-12-30
申请号：US12099175
申请日：2008-04-08
申请人： Alan B. Botula , Alvin J. Joseph , Stephen E. Luce , John J. Pekarik , Yun Shi
发明人： Alan B. Botula , Alvin J. Joseph , Stephen E. Luce , John J. Pekarik , Yun Shi
IPC分类号： H01L21/336 , H01L29/417 , H01L29/66
CPC分类号： H01L29/7834 , H01L29/0847 , H01L29/41783 , H01L29/423 , H01L29/66575
摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.
摘要翻译：提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。有源区具有不同于第一导电类型的第二导电类型。接触区域与有源区域电接触。该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。

10. 发明授权

US08633082B2 Method for fabricating high-gain MOSFETs with asymmetric source/drain doping for analog and RF applications 失效
标题翻译：用于制造模拟和RF应用的具有不对称源/漏掺杂的高增益MOSFET的方法
公开(公告)号：US08633082B2
公开(公告)日：2014-01-21
申请号：US13302432
申请日：2011-11-22
申请人： Sebastien Lasserre , John J. Pekarik
发明人： Sebastien Lasserre , John J. Pekarik
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/66772 , H01L21/26586 , H01L27/105 , H01L27/1104 , H01L29/1083 , H01L29/66659
摘要： A method of fabrication of an analog, asymmetric Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) is provided. The method may comprise forming a first gate oriented in a first direction over an active region of a semiconductor substrate, forming a second gate extending perpendicular to the first gate over a second active region, using a dual-directional implant process to form a reduced-HALO doped area on a drain side of the first gate and also for a HALO doped area for the second gate, while the source side of the first gate is covered by a resist. Additionally, the method may comprise forming a HALO doped area on the source side of the first gate using a quad-directional implant process using the mask also used for HALO implants of other digital-logic devices on the substrate, while the drain side of the gate is blocked by a resist.
摘要翻译：提供了一种制造模拟非对称金属氧化物半导体场效应晶体管（MOSFET）的方法。该方法可以包括在半导体衬底的有源区上形成在第一方向上取向的第一栅极，在第二有源区上形成垂直于第一栅极延伸的第二栅极，使用双向注入工艺，第一栅极的漏极侧的HALO掺杂区域以及用于第二栅极的HALO掺杂区域，而第一栅极的源极侧被抗蚀剂覆盖。另外，该方法可以包括使用四面体注入工艺在第一栅极的源极侧上形成HALO掺杂区域，其使用也用于衬底上的其它数字逻辑器件的HALO注入的掩模，而漏极侧门被抗蚀剂阻挡。

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