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1. 发明申请

US20140035064A1 SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE 有权
标题翻译：半导体结构和制造方法
公开(公告)号：US20140035064A1
公开(公告)日：2014-02-06
申请号：US13566404
申请日：2012-08-03
申请人： William F. CLARK, JR. , Qizhi LIU , John J. Pekarik , Yun SHI , Yanli ZHANG
发明人： William F. CLARK, JR. , Qizhi LIU , John J. Pekarik , Yun SHI , Yanli ZHANG
IPC分类号： H01L21/8249 , H01L27/06
CPC分类号： H01L27/0623 , H01L21/823418 , H01L21/8249 , H01L27/088 , H01L27/0922 , H01L29/04 , H01L29/161 , H01L29/402 , H01L29/45 , H01L29/66659 , H01L29/7302 , H01L29/735 , H01L29/78 , H01L29/7817 , H01L29/7835
摘要： Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.
摘要翻译：本文公开了半导体结构和制造方法。具体地，本文公开了制造高压金属氧化物半导体场效应晶体管和各种结构的方法。一种方法包括在FET区域的衬底上形成场效应晶体管（FET），在HVFET区域中的过掺杂掺杂扩散（LDD）漏极上的介质堆叠上形成高电压FET（HVFET），以及在NPN区域的基板上形成NPN。

2. 发明申请

US20130168822A1 SELF ALIGNED STRUCTURES AND DESIGN STRUCTURE THEREOF 失效
标题翻译：自对准结构及其设计结构
公开(公告)号：US20130168822A1
公开(公告)日：2013-07-04
申请号：US13343287
申请日：2012-01-04
申请人： William F. CLARK, JR. , John J. PEKARIK , Yun SHI , Yanli ZHANG
发明人： William F. CLARK, JR. , John J. PEKARIK , Yun SHI , Yanli ZHANG
IPC分类号： H01L29/732 , G06F17/50 , H01L21/331
CPC分类号： H01L29/66272 , H01L21/8249 , H01L21/84 , H01L27/1203 , H01L29/732
摘要： Vertical bipolar junction structures, methods of manufacture and design structures. The method includes forming one or more sacrificial structures for a bipolar junction transistor (BJT) in a first region of a chip. The method includes forming a mask over the one or more sacrificial structures. The method further includes etching an opening in the mask, aligned with the one or more sacrificial structures. The method includes forming a trench through the opening and extending into diffusion regions below the one or more sacrificial structures. The method includes forming a base region of the BJT by depositing an epitaxial material in the trench, in contact with the diffusion regions. The method includes forming an emitter contact by depositing a second epitaxial material on the base region within the trench. The epitaxial material for the emitter region is of an opposite dopant type than the epitaxial material of the base region.
摘要翻译：垂直双极结结构，制造方法和设计结构。该方法包括在芯片的第一区域中形成用于双极结型晶体管（BJT）的一个或多个牺牲结构。该方法包括在一个或多个牺牲结构上形成掩模。该方法还包括蚀刻掩模中与该一个或多个牺牲结构对准的开口。该方法包括通过该开口形成沟槽并延伸到一个或多个牺牲结构下方的扩散区域中。该方法包括通过在沟槽中沉积与扩散区接触的外延材料来形成BJT的基极区域。该方法包括通过在沟槽内的基极区域上沉积第二外延材料来形成发射极接触。用于发射极区域的外延材料具有与基极区域的外延材料相反的掺杂剂类型。

3. 发明申请

US20120064694A1 FORMING IMPLANTED PLATES FOR HIGH ASPECT RATIO TRENCHES USING STAGED SACRIFICIAL LAYER REMOVAL 失效
标题翻译：使用标准的真空层去除形成用于高比例斜率的植入板
公开(公告)号：US20120064694A1
公开(公告)日：2012-03-15
申请号：US12880419
申请日：2010-09-13
申请人： Roger A. BOOTH, JR. , Kangguo CHENG , Joseph ERVIN , Chengwen PEI , Ravi M. TODI , Geng WANG , Yanli ZHANG
发明人： Roger A. BOOTH, JR. , Kangguo CHENG , Joseph ERVIN , Chengwen PEI , Ravi M. TODI , Geng WANG , Yanli ZHANG
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , H01L27/1087
摘要： A method of forming a deep trench structure for a semiconductor device includes forming a mask layer over a semiconductor substrate. An opening in the mask layer is formed by patterning the mask layer, and a deep trench is formed in the semiconductor substrate using the patterned opening in the mask layer. A sacrificial fill material is formed over the mask layer and into the deep trench. A first portion of the sacrificial fill material is recessed from the deep trench and a first dopant implant forms a first doped region in the semiconductor substrate. A second portion of the sacrificial fill material is recessed from the deep trench and a second dopant implant forms a second doped region in the semiconductor substrate, wherein the second doped region is formed underneath the first doped region such that the second doped region and the first doped region are contiguous with each other.
摘要翻译：形成半导体器件的深沟槽结构的方法包括在半导体衬底上形成掩模层。通过对掩模层进行构图来形成掩模层中的开口，并且使用掩模层中的图案化开口在半导体衬底中形成深沟槽。牺牲填充材料形成在掩模层上并进入深沟槽中。牺牲填充材料的第一部分从深沟槽凹陷，并且第一掺杂剂注入在半导体衬底中形成第一掺杂区域。牺牲填充材料的第二部分从深沟槽凹陷，并且第二掺杂剂注入在半导体衬底中形成第二掺杂区，其中第二掺杂区形成在第一掺杂区的下方，使得第二掺杂区和第一掺杂区掺杂区域彼此邻接。

4. 发明申请

US20110316061A1 STRUCTURE AND METHOD TO CONTROL BOTTOM CORNER THRESHOLD IN AN SOI DEVICE 有权
标题翻译：在SOI器件中控制底部拐角阈值的结构和方法
公开(公告)号：US20110316061A1
公开(公告)日：2011-12-29
申请号：US12822492
申请日：2010-06-24
申请人： Joseph ERVIN , Jeffrey B. JOHNSON , Kevin MCSTAY , Paul C. PARRIES , Chengwen PEI , Geng WANG , Yanli ZHANG
发明人： Joseph ERVIN , Jeffrey B. JOHNSON , Kevin MCSTAY , Paul C. PARRIES , Chengwen PEI , Geng WANG , Yanli ZHANG
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L21/76237 , H01L27/10847 , H01L27/1203
摘要： Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.
摘要翻译：半导体结构和方法来控制绝缘体上硅（SOI）器件中的底角阈值。一种方法包括掺杂绝缘体上半导体（SOI）岛的角区域。掺杂包括定制角区域的局部掺杂以减少SOI岛与相邻结构的电容耦合。

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