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1. 发明授权

US5482878A Method for fabricating insulated gate field effect transistor having subthreshold swing 失效
标题翻译：具有亚阈值摆幅的绝缘栅场效应晶体管的制造方法
公开(公告)号：US5482878A
公开(公告)日：1996-01-09
申请号：US223393
申请日：1994-04-04
申请人： Vida I. Burger , Michael H. Kaneshiro , Diann Dow , Kevin M. Klein , Michael P. Masquelier , E. James Prendergast
发明人： Vida I. Burger , Michael H. Kaneshiro , Diann Dow , Kevin M. Klein , Michael P. Masquelier , E. James Prendergast
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78 , H01L21/265
CPC分类号： H01L27/0928 , H01L21/823807 , H01L29/7835
摘要： Insulated gate field effect transistors (10, 70) having process steps for setting the V.sub.T and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a unilateral transistor (10), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the V.sub.T and the device leakage current. A halo region (34, 39) contains the source region (48, 51) and sets the punchthrough voltage. In a bilateral transistor (70), both a source region (83, 86) and a drain region (84, 87) are contained within halo regions (75, 74, 79, 81). A portion (76, 82) of a dopant layer (25, 30) sets the V.sub.T and a leakage current, whereas the halo region (75, 79) sets the punchthrough voltage.
摘要翻译：绝缘栅场效应晶体管（10,70）具有用于设置VT和器件漏电流的工艺步骤，所述工艺步骤与用于提供穿透保护的工艺步骤分离，从而降低亚阈值摆幅。在单侧晶体管（10）中，源极区（48,51）和漏极区（49,52）之间的掺杂剂层（25,30）的部分（37,45）用作沟道区域，并将 VT和器件漏电流。光晕区域（34,39）包含源极区域（48,51）并设置穿透电压。在双向晶体管（70）中，源极区域（83,86）和漏极区域（84,87）都包含在光晕区域（75,74,79,81）内。掺杂剂层（25,30）的一部分（76,82）设定VT和漏电流，而光晕区域（75,79）设定穿透电压。

2. 发明授权

US09502890B2 Protection device and related fabrication methods 有权
标题翻译：保护装置及相关制造方法
公开(公告)号：US09502890B2
公开(公告)日：2016-11-22
申请号：US13900226
申请日：2013-05-22
申请人： Rouying Zhan , Chai Ean Gill , Wen-Yi Chen , Michael H. Kaneshiro
发明人： Rouying Zhan , Chai Ean Gill , Wen-Yi Chen , Michael H. Kaneshiro
IPC分类号： H01L29/66 , H01L27/02 , H02H9/04 , H01L29/732
CPC分类号： H02H9/044 , H01L27/0259 , H01L29/7322 , H02H9/046
摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region.
摘要翻译：提供了保护装置结构和相关制造方法。一种示例性的半导体保护装置包括具有第一导电类型的半导体材料的第一基极区域，具有第一导电类型的第二基极区域和具有小于第一基极区域的掺杂剂浓度的第二基极区域，半导体的第三基极区域具有第一导电类型和大于第二基极区的掺杂剂浓度的材料，具有与第一基极区内的第一导电类型相反的第二导电类型的半导体材料的发射极区域和具有第一导电类型的半导体材料的集电极区域，第二导电类型。第二基极区域的至少一部分位于第三基极区域和第一基极区域之间，并且第一基极区域的至少一部分位于发射极区域和集电极区域之间。

3. 发明申请

US20160005730A1 ESD Protection with Asymmetrical Bipolar-Based Device 有权
标题翻译：使用不对称双极性器件的ESD保护
公开(公告)号：US20160005730A1
公开(公告)日：2016-01-07
申请号：US14854366
申请日：2015-09-15
申请人： Rouying Zhan , Chai Ean Gill , Changsoo Hong , Michael H. Kaneshiro
发明人： Rouying Zhan , Chai Ean Gill , Changsoo Hong , Michael H. Kaneshiro
IPC分类号： H01L27/02 , H01L27/082 , H01L29/08 , H01L29/10 , H01L29/66 , H01L29/06
CPC分类号： H01L27/0259 , H01L23/60 , H01L27/0248 , H01L27/0262 , H01L27/082 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/66234 , H01L29/6625 , H01L29/73 , H01L29/7317 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.
摘要翻译：在包括具有第一导电类型的半导体层的半导体衬底中制造ESD保护器件。第一阱注入程序在半导体层中注入第二导电类型的掺杂剂以形成内部和外部沉降片区域。内沉陷区域被配置成建立第一和第二双极晶体管器件的公共集电极区域。第二阱注入步骤在半导体层中注入第一导电类型的掺杂剂以形成第一和第二双极晶体管器件的相应基极区。第一双极晶体管器件的导通由第一双极晶体管器件的内部沉降区域和基极区域之间的击穿触发。第二双极晶体管器件的导通由第二双极晶体管器件的外部沉降区域和基极区域之间的击穿触发。

4. 发明授权

US09129806B2 Protection device and related fabrication methods 有权
标题翻译：保护装置及相关制造方法
公开(公告)号：US09129806B2
公开(公告)日：2015-09-08
申请号：US13900256
申请日：2013-05-22
申请人： Rouying Zhan , Chai Ean Gill , Wen-Yi Chen , Michael H. Kaneshiro
发明人： Rouying Zhan , Chai Ean Gill , Wen-Yi Chen , Michael H. Kaneshiro
IPC分类号： H01L29/74 , H01L29/66 , H01L27/02
CPC分类号： H01L27/0259
摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage.
摘要翻译：提供了保护装置结构和相关制造方法。示例性的半导体保护装置包括具有第一导电类型的基极阱区域，在基极阱区域内的发射极区域具有与第一导电类型相反的第二导电类型，具有第二导电类型的集电极区域，具有第二导电类型的第一浮动区域，在发射极区域和集电极区域之间的基极阱区域内的第二导电类型，以及在第一浮动区域和集电极区域之间的基极阱区域内具有第一导电类型的第二浮动区域。基极区域内的浮动区域电连接以减小电流增益并改善保持电压。

5. 发明申请

US20150102384A1 ESD Protection with Asymmetrical Bipolar-Based Device 有权
标题翻译：使用不对称双极性器件的ESD保护
公开(公告)号：US20150102384A1
公开(公告)日：2015-04-16
申请号：US14053716
申请日：2013-10-15
申请人： Rouying Zhan , Chai Ean Gill , Changsoo Hong , Michael H. Kaneshiro
发明人： Rouying Zhan , Chai Ean Gill , Changsoo Hong , Michael H. Kaneshiro
IPC分类号： H01L27/02 , H01L23/60 , H01L29/66
CPC分类号： H01L27/0259 , H01L23/60 , H01L27/0248 , H01L27/0262 , H01L27/082 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/66234 , H01L29/6625 , H01L29/73 , H01L29/7317 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device.
摘要翻译：静电放电（ESD）保护装置包括半导体衬底，该半导体衬底包括掩埋绝缘体层和在具有第一导电类型的掩埋绝缘体层上的半导体层，以及设置在半导体层中的彼此横向间隔开的第一和第二双极晶体管器件并且共享具有第二导电类型的公共收集器区域。第一和第二双极晶体管器件被配置成非对称布置，其中第二双极晶体管器件包括具有第二导电类型的掩埋掺杂层，并且沿着埋在绝缘体层的跨第二极二极管的器件区域的公共集电极区域延伸晶体管器件。

6. 发明授权

US6017798A FET with stable threshold voltage and method of manufacturing the same 失效
标题翻译：具有稳定阈值电压的FET及其制造方法
公开(公告)号：US6017798A
公开(公告)日：2000-01-25
申请号：US865846
申请日：1997-06-02
申请人： Vida Ilderem , Michael H. Kaneshiro , Diann Dow
发明人： Vida Ilderem , Michael H. Kaneshiro , Diann Dow
IPC分类号： H01L29/78 , H01L21/336 , H01L29/08 , H01L29/10
CPC分类号： H01L29/6659 , H01L29/0847 , H01L29/1045 , H01L29/665 , H01L29/6656 , H01L29/66659
摘要： A low voltage field effect transistor structure (20) is provided with a threshold voltage that is tolerant of process variations that alter the location of a source implant region (41). A first halo region (33) and a second halo region (36) are formed adjacent to source region (41) such that after subsequent thermal processing, a constant doping profile of opposite conductivity as source region (41) is formed in the channel region (23) adjacent the source region (41). The embodiments can be formed either adjacent to only the source region (41) to create a unilateral device, or the doping profile can be formed adjacent to both source region (41) and a drain region (40) to produce a bilateral device. An additional embodiment forms a second implant region in source region (41) to reduce junction leakage and capacitance.
摘要翻译：低电压场效应晶体管结构（20）被提供有允许改变源植入区域（41）的位置的工艺变化的阈值电压。形成与源区（41）相邻的第一晕区（33）和第二晕区（36），使得在随后的热处理之后，在通道区域（41）中形成具有与源区（41）相反的导电性的恒定掺杂分布（23），邻近源极区域（41）。实施例可以形成为仅与源极区域（41）相邻以产生单侧器件，或者可以在源极区域（41）和漏极区域（40）附近形成掺杂分布以产生双边器件。另外的实施例在源区（41）中形成第二注入区以减少结漏电流。

7. 发明授权

US5427964A Insulated gate field effect transistor and method for fabricating 失效
标题翻译：绝缘栅场效应晶体管及其制造方法
公开(公告)号：US5427964A
公开(公告)日：1995-06-27
申请号：US223394
申请日：1994-04-04
申请人： Michael H. Kaneshiro , Diann Dow
发明人： Michael H. Kaneshiro , Diann Dow
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L21/265
CPC分类号： H01L29/66659 , H01L21/823807
摘要： Insulated gate field effect transistors (10, 70) having independent process steps for setting lateral and vertical dopant profiles for source and drain regions. In a unilateral transistor (10) , portions (48, 50, 51, 55) of the source region are contained within a halo region (34, 41) whereas portions (49, 47, 52, 64) of the drain region are non contained within a halo region. The source region (60, 65) has a first portion (48, 51) for setting a channel length and a second portion (50, 55 ) for setting a breakdown voltage and a source/drain capacitance. The second portion (50, 55) extends further into the halo region than the first portion (48, 51). In a bilateral transistor (70), portions (84, 89, 90, 91) of the drain region (72, 87) are contained within halo region (75, 79 ).
摘要翻译：绝缘栅场效应晶体管（10,70）具有用于设置源极和漏极区域的横向和垂直掺杂物分布的独立工艺步骤。在单侧晶体管（10）中，源极区域的部分（48,50,51,55）包含在卤素区域（34,41）内，而漏极区域的部分（49,47,52,64）不是包含在光晕区域内。源区域（60,65）具有用于设定沟道长度的第一部分（48,51）和用于设置击穿电压和源极/漏极电容的第二部分（50,55）。第二部分（50,55）比第一部分（48,51）进一步延伸到晕圈区域。在双向晶体管（70）中，漏极区域（72,87）的部分（84,89,90,91）包含在光晕区域（75,79）内。

8. 发明授权

US5083466A Multidimensional force sensor 失效
标题翻译：多维力传感器
公开(公告)号：US5083466A
公开(公告)日：1992-01-28
申请号：US522528
申请日：1990-05-11
申请人： James W. Holm-Kennedy , Gordon P. Lee , Michael H. Kaneshiro
发明人： James W. Holm-Kennedy , Gordon P. Lee , Michael H. Kaneshiro
IPC分类号： G01P15/08 , G01P15/12 , G01P15/125 , G01P15/18 , G01L5/16
CPC分类号： G01P15/125 , G01P15/0802 , G01P15/123 , G01P15/18 , G01P2015/0817 , G01P2015/0828
摘要： A multibeam structure measures displacement of one or more response elements to detect multiple components of applied force. The flexible beams are each coupled to a response element which may be displaced by a force arising from linear acceleration, angular acceleration, fluid flow, electric/magnetic/gravitational fields, and others sources. The displacement of the response element is detected with a variety of sensing methods including capacitive and piezoresistive sensing.
摘要翻译：多光束结构测量一个或多个响应元件的位移以检测施加的力的多个分量。柔性梁各自耦合到响应元件，该响应元件可以由线性加速度，角加速度，流体流动，电/磁/重力场等来源产生的力移位。响应元件的位移通过包括电容和压阻感测的各种感测方法来检测。

9. 发明授权

US09177952B2 ESD protection with asymmetrical bipolar-based device 有权
标题翻译：使用非对称双极型器件的ESD保护
公开(公告)号：US09177952B2
公开(公告)日：2015-11-03
申请号：US14053716
申请日：2013-10-15
申请人： Rouying Zhan , Chai Ean Gill , Changsoo Hong , Michael H. Kaneshiro
发明人： Rouying Zhan , Chai Ean Gill , Changsoo Hong , Michael H. Kaneshiro
IPC分类号： H01L29/74 , H01L29/747 , H01L29/00 , H01L21/331 , H01L27/082 , H01L29/73 , H01L27/02 , H01L29/66 , H01L23/60
CPC分类号： H01L27/0259 , H01L23/60 , H01L27/0248 , H01L27/0262 , H01L27/082 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/66234 , H01L29/6625 , H01L29/73 , H01L29/7317 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device.
摘要翻译：静电放电（ESD）保护装置包括半导体衬底，该半导体衬底包括掩埋绝缘体层和在具有第一导电类型的掩埋绝缘体层上的半导体层，以及设置在半导体层中的彼此横向间隔开的第一和第二双极晶体管器件并且共享具有第二导电类型的公共收集器区域。第一和第二双极晶体管器件被配置成非对称布置，其中第二双极晶体管器件包括具有第二导电类型的掩埋掺杂层，并且沿着埋在绝缘体层的跨第二极二极管的器件区域的公共集电极区域延伸晶体管器件。

10. 发明申请

US20140347771A1 PROTECTION DEVICE AND RELATED FABRICATION METHODS 有权
标题翻译：保护装置及相关制造方法
公开(公告)号：US20140347771A1
公开(公告)日：2014-11-27
申请号：US13900226
申请日：2013-05-22
申请人： Rouying ZHAN , Chai Ean GILL , Wen-Yi CHEN , Michael H. KANESHIRO
发明人： Rouying ZHAN , Chai Ean GILL , Wen-Yi CHEN , Michael H. KANESHIRO
IPC分类号： H01L29/74 , H02H9/04 , H01L29/66
CPC分类号： H02H9/044 , H01L27/0259 , H01L29/7322 , H02H9/046
摘要： Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region.
摘要翻译：提供了保护装置结构和相关制造方法。一种示例性的半导体保护装置包括具有第一导电类型的半导体材料的第一基极区域，具有第一导电类型的第二基极区域和具有小于第一基极区域的掺杂剂浓度的第二基极区域，半导体的第三基极区域具有第一导电类型和大于第二基极区的掺杂剂浓度的材料，具有与第一基极区内的第一导电类型相反的第二导电类型的半导体材料的发射极区域和具有第一导电类型的半导体材料的集电极区域，第二导电类型。第二基极区域的至少一部分位于第三基极区域和第一基极区域之间，并且第一基极区域的至少一部分位于发射极区域和集电极区域之间。

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