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1. 发明申请

US20130071998A1 Electrical Fuse With Metal Line Migration 审中-公开
标题翻译：具有金属线迁移的电气保险丝
公开(公告)号：US20130071998A1
公开(公告)日：2013-03-21
申请号：US13234205
申请日：2011-09-16
申请人： Baozhen Li , Yan Zun Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Baozhen Li , Yan Zun Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/326 , H01L21/28 , H01L23/52
CPC分类号： H01L23/5256 , H01L21/326 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element.
摘要翻译：公开了一种电熔丝装置。电路装置可以包括熔丝装置，第一电路元件和第二电路元件。熔丝包括具有第一电迁移电阻的第一触点，具有第二电迁移电阻的第二触点和耦合到第一触点和第二触点的金属线，其具有低于第二次电迁移阻力。第一电路元件耦合到第一触点，而第二电路元件耦合到第二触点。保险丝被配置为通过金属线将编程电流从第一触点传导到第二触点。此外，编程电流使金属线电离远离第二触点，以将第二电路元件与第一电路元件电隔离。

2. 发明授权

US11152300B2 Electrical fuse with metal line migration 有权
公开(公告)号：US11152300B2
公开(公告)日：2021-10-19
申请号：US13234205
申请日：2011-09-16
申请人： Baozhen Li , Yan Zun Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Baozhen Li , Yan Zun Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/525 , H01L21/326
摘要： An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element.

3. 发明申请

US20130328167A1 SELF-ALIGNED METAL-INSULATOR-METAL (MIM) CAPACITOR 审中-公开
标题翻译：自对准金属绝缘子 - 金属（MIM）电容器
公开(公告)号：US20130328167A1
公开(公告)日：2013-12-12
申请号：US13489940
申请日：2012-06-06
申请人： Chih-Chao Yang , Daniel C. Edelstein , Baozhen Li , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Daniel C. Edelstein , Baozhen Li , Keith Kwong Hon Wong
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/75 , H01L23/5223 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure integrated within a back-end-of-the-line (BEOL) structure is provided. The MIM capacitor structure includes a lower electrode, i.e., a first conductive material, embedded within a dielectric material of the BEOL structure, a dielectric material liner having a dielectric constant of equal to, or greater than, silicon dioxide located atop the lower electrode, and an upper electrode, i.e., a second conductive material, positioned between vertical portions of the dielectric material liner and atop a horizontal connecting portion of the dielectric material liner. In accordance with the present disclosure, the vertical portions of the dielectric material liner do not extend onto an upper surface of the dielectric material that includes the lower electrode.
摘要翻译：提供集成在后端（BEOL）结构中的金属 - 绝缘体 - 金属（MIM）电容器结构。 MIM电容器结构包括嵌入在BEOL结构的电介质材料中的下电极，即第一导电材料，具有等于或大于位于下电极顶部的二氧化硅的介电常数的介电材料衬垫，以及位于电介质材料衬垫的垂直部分之间并且位于介电材料衬里的水平连接部分顶部的上电极，即第二导电材料。根据本公开，电介质材料衬垫的垂直部分不延伸到包括下电极的电介质材料的上表面上。

4. 发明申请

US20140048927A1 METHOD TO IMPROVE FINE CU LINE RELIABILITY IN AN INTEGRATED CIRCUIT DEVICE 有权
标题翻译：在集成电路设备中提高精细线路可靠性的方法
公开(公告)号：US20140048927A1
公开(公告)日：2014-02-20
申请号：US13587998
申请日：2012-08-17
申请人： Chad M. Burke , Baozhen Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Chad M. Burke , Baozhen Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76847 , H01L21/76838 , H01L21/76843 , H01L21/76844 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers.
摘要翻译：用于形成半导体结构的结构和方法。半导体结构包括包括至少一个铜互连层的多个层。铜互连层在半导体结构中的物理相邻层之一和半导体结构中的集成电路和电子器件之间提供电导体。多个螺柱被定位在所述至少一个铜互连层内。螺栓间隔开小于或等于至少一个铜互连层的Blech长度的距离。漂浮长度是低于该值的长度，在该长度之下不会发生由于至少一个铜互连层内的金属原子的电迁移而导致的损伤。多个螺柱包括铜原子扩散阻挡层。

5. 发明授权

US09224640B2 Method to improve fine Cu line reliability in an integrated circuit device 有权
标题翻译：提高集成电路器件中Cu线可靠性的方法
公开(公告)号：US09224640B2
公开(公告)日：2015-12-29
申请号：US13587998
申请日：2012-08-17
申请人： Chad M. Burke , Baozhen Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Chad M. Burke , Baozhen Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528 , H01L23/522
CPC分类号： H01L21/76847 , H01L21/76838 , H01L21/76843 , H01L21/76844 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers.
摘要翻译：用于形成半导体结构的结构和方法。半导体结构包括包括至少一个铜互连层的多个层。铜互连层在半导体结构中的物理相邻层之一和半导体结构中的集成电路和电子器件之间提供电导体。多个螺柱被定位在所述至少一个铜互连层内。螺栓间隔开小于或等于至少一个铜互连层的Blech长度的距离。漂浮长度是低于该值的长度，在该长度之下不会发生由于至少一个铜互连层内的金属原子的电迁移而导致的损伤。多个螺柱包括铜原子扩散阻挡层。

6. 发明授权

US08815734B2 Use of gas cluster ion beam to reduce metal void formation in interconnect structures 有权
标题翻译：使用气体簇离子束来减少互连结构中的金属空隙形成
公开(公告)号：US08815734B2
公开(公告)日：2014-08-26
申请号：US13290577
申请日：2011-11-07
申请人： Kangguo Cheng , Junli Wang , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Kangguo Cheng , Junli Wang , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76804 , H01L21/76814 , H01L21/76825 , H01L21/76865 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material.
摘要翻译：使用气体簇离子束工艺来减少和/或甚至消除互连结构中的金属空隙形成。在一个实施例中，气体簇离子束蚀刻在互连电介质材料中形成倒角开口。在另一个实施方案中，气体簇离子束蚀刻减少扩散阻挡层或扩散阻挡层的多层堆叠和形成在位于互连电介质材料中的开口内的电镀种子层的悬垂分布。在另一个实施例中，气体团簇离子束过程使位于其中形成的开口的上角的互连电介质材料的表面失活。在该实施例中，气体簇离子束处理沉积了使形成为互连电介质材料的每个开口的上角失活的材料。

7. 发明授权

US08421228B2 Structure and methods of forming contact structures 有权
标题翻译：形成接触结构的结构和方法
公开(公告)号：US08421228B2
公开(公告)日：2013-04-16
申请号：US13405443
申请日：2012-02-27
申请人： Ying Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Ying Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76846 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A contact structure and a method of forming the contact structure. The structure includes: a silicide layer on and in direct physical contact with a top substrate surface of a substrate; an electrically insulating layer on the substrate; and an aluminum plug within the insulating layer. The aluminum plug has a thickness not exceeding 25 nanometers in a direction perpendicular to the top substrate surface. The aluminum plug extends from a top surface of the silicide layer to a top surface of the insulating layer. The aluminum plug is in direct physical contact with the top surface of the silicide layer and is in direct physical contact with the silicide layer. The method includes: forming the silicide layer on and in direct physical contact with the top substrate surface of the substrate; forming the electrically insulating layer on the substrate; and forming the aluminum plug within the insulating layer.
摘要翻译：接触结构和形成接触结构的方法。该结构包括：与衬底的顶部衬底表面直接物理接触的硅化物层; 基板上的电绝缘层; 和绝缘层内的铝塞。该铝塞的垂直于顶部基板表面的方向的厚度不超过25纳米。铝塞从硅化物层的顶表面延伸到绝缘层的顶表面。铝插塞与硅化物层的顶表面直接物理接触并与硅化物层直接物理接触。该方法包括：在衬底的顶部衬底表面上直接物理接触形成硅化物层; 在基板上形成电绝缘层; 以及在所述绝缘层内形成所述铝塞。

8. 发明授权

US08183145B2 Structure and methods of forming contact structures 有权
标题翻译：形成接触结构的结构和方法
公开(公告)号：US08183145B2
公开(公告)日：2012-05-22
申请号：US11870551
申请日：2007-10-11
申请人： Ying Li , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Ying Li , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76846 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; depositing an electrically conductive layer covering a bottom and at least one vertical wall of the via; removing the conductive layer from the bottom; and filling the via with aluminum directly contacting the silicide layer. A structure includes: a silicide layer disposed on a substrate; an electrically insulating layer disposed over the silicide layer; an aluminum plug extending through the insulating layer and directly contacting the silicide layer; and an electrically conductive layer disposed between the plug and the insulating layer. Also included is a method where an aluminum layer grows selectively from a silicide layer and at least one sidewall of a trench.
摘要翻译：方法和结构。形成接触结构的方法包括将硅化物层沉积到基底上; 在所述硅化物层的第一表面上沉积电绝缘层; 通过延伸到第一表面的绝缘层形成通孔; 沉积覆盖所述通孔的底部和至少一个垂直壁的导电层; 从底部去除导电层; 并且用直接与硅化物层接触的铝填充该通孔。一种结构包括：设置在基板上的硅化物层; 设置在所述硅化物层上的电绝缘层; 延伸穿过绝缘层并直接接触硅化物层的铝塞; 以及设置在插塞和绝缘层之间的导电层。还包括其中铝层从硅化物层和沟槽的至少一个侧壁选择性地生长的方法。

9. 发明申请

US20100143649A1 HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD 有权
标题翻译：高比例电镀金属特征及方法
公开(公告)号：US20100143649A1
公开(公告)日：2010-06-10
申请号：US12706108
申请日：2010-02-16
申请人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
发明人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
IPC分类号： B32B3/10
CPC分类号： C25D5/02 , Y10T428/24331 , Y10T428/24917
摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.
摘要翻译：公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料没有接缝和/或空隙。此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

10. 发明申请

US20090111235A1 Semiconductor Integrated Circuit Devices Having High-Q Wafer Back-Side Capacitors 有权
标题翻译：具有高Q晶片背面电容器的半导体集成电路器件
公开(公告)号：US20090111235A1
公开(公告)日：2009-04-30
申请号：US12348707
申请日：2009-01-05
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/02
CPC分类号： H01L21/84 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

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