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    • 1. 发明授权
    • Pre-bias control for switched mode power supplies
    • 开关模式电源的预偏置控制
    • US08803495B2
    • 2014-08-12
    • US12846370
    • 2010-07-29
    • Baoson NguyenRex M. TeggatzLi Li
    • Baoson NguyenRex M. TeggatzLi Li
    • H02M1/36
    • H02M1/36H02M3/1588Y02B70/1466
    • An embodiment of the invention provides a method of reducing a drop in voltage on a pre-biased output of a DC-DC step-down switching converter. A high side switch is activated to conduct a first current to the pre-biased output. After the high side switch is activated, a low side switch is activated to draw a second current from the pre-biased output such that the magnitude of the first current is greater than the magnitude of the second current for at least a portion of a time period T1. After the time period T1 ends, the magnitudes of the first and second currents are changed to maintain a predetermined voltage on the pre-biased output.
    • 本发明的实施例提供了一种降低DC-DC降压开关转换器的预偏置输出上的电压降的方法。 激活高侧开关以将第一电流传导到预偏置输出。 在高侧开关被激活之后,低侧开关被激活以从预偏置输出中抽出第二电流,使得第一电流的大小在至少一部分时间内大于第二电流的大小 期T1。 在时间段T1结束之后,改变第一和第二电流的大小以在预偏置输出上保持预定的电压。
    • 3. 发明授权
    • Programmable voltage regulator configurable for double power density and reverse blocking
    • 可编程稳压器可配置双功率密度和反向阻塞
    • US07071664B1
    • 2006-07-04
    • US11017177
    • 2004-12-20
    • Ross E. TeggatzSanmukh M. PatelRex M. TeggatzSuribhotla V. RajasekharValerian Mayega
    • Ross E. TeggatzSanmukh M. PatelRex M. TeggatzSuribhotla V. RajasekharValerian Mayega
    • G05F1/44
    • H02J7/0063
    • A programmable voltage regulator configurable for reverse blocking and double power density is disclosed herein. The programmable voltage regulator includes an error amplifier that couples to receive a reference voltage. A first NMOS pass transistor connects between an auxiliary voltage input node and the output terminal of the voltage regulator, wherein the first NMOS pass transistor is biased by the output of the error amplifier. Connected between the source of the first NMOS pass transistor and the second input of the error amplifier, a feedback network provides feedback for the voltage regulator. A second NMOS pass transistor connects between the first power supply and the auxiliary voltage input node. Furthermore, an independent node control circuit biases the second NMOS pass transistor such that in a first mode of operation, a first control signal input is operable to receive a signal for controlling the second NMOS pass transistor during reverse battery condition. In a second mode of operation, independent node control circuit includes a second control signal input that is operable to couple to the output terminal of the error amplifier while simultaneously the first power supply rail is operable to couple to the output terminal of the voltage regulator to provide double power density.
    • 本文公开了可配置用于反向阻塞和双功率密度的可编程电压调节器。 可编程电压调节器包括耦合以接收参考电压的误差放大器。 第一NMOS传输晶体管连接在辅助电压输入节点和电压调节器的输出端之间,其中第一NMOS传输晶体管被误差放大器的输出偏置。 连接在第一NMOS传输晶体管的源极和误差放大器的第二输入端之间,反馈网络为电压调节器提供反馈。 第二NMOS传输晶体管连接在第一电源和辅助电压输入节点之间。 此外,独立节点控制电路偏置第二NMOS传输晶体管,使得在第一操作模式中,第一控制信号输入可操作以在反向电池状态期间接收用于控制第二NMOS传输晶体管的信号。 在第二操作模式中,独立节点控制电路包括第二控制信号输入,其可操作以耦合到误差放大器的输出端,同时第一电源轨可操作以耦合到电压调节器的输出端, 提供双倍功率密度。
    • 6. 发明授权
    • Current limited power MOSFET device with improved safe operating area
    • 电流限制功率MOSFET器件,具有改进的安全工作区域
    • US06169439A
    • 2001-01-02
    • US09000825
    • 1997-12-30
    • Ross TeggatzDavid J. BaldwinRex M. Teggatz
    • Ross TeggatzDavid J. BaldwinRex M. Teggatz
    • H03K508
    • H03K17/0822
    • An integrated circuit having a protected output field effect transistor (FET) (101). A drain-gate clamp circuit (105) is coupled to divert charge from the power FET drain electrode to the power FET gate electrode when excessive drain-source voltage is present. A drain-source current limit circuit (110) is coupled to divert charge from the power FET gate electrode to the power FET source electrode when a preselected drain-source current is achieved. A current limit inhibit circuit (115) is coupled between the current limit circuit and the power FET gate electrode, and having a control electrode coupled to the drain-gate clamp circuit. The current limit inhibit circuit (115) disables the current limit circuit (110) when charge flows in the drain-gate clamp circuit (105).
    • 具有受保护的输出场效应晶体管(FET)(101)的集成电路。 当存在过多的漏极 - 源极电压时,漏极 - 栅极钳位电路(105)被耦合以将电荷从功率FET漏电极转移到功率FET栅电极。 当预定的漏极 - 源极电流达到时,漏极 - 源极限流电路(110)被耦合以将电荷从功率FET栅电极转移到功率FET源电极。 电流限制抑制电路(115)耦合在限流电路和功率FET栅电极之间,并且具有耦合到漏极 - 栅极钳位电路的控制电极。 当漏极 - 门极钳位电路(105)中的电荷流动时,电流限制禁止电路(115)禁用限流电路(110)。