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1. 发明授权

US06559019B1 Breakdown drain extended NMOS 有权
标题翻译：击穿漏极扩展NMOS
公开(公告)号：US06559019B1
公开(公告)日：2003-05-06
申请号：US09572785
申请日：2000-05-17
申请人： Baoson Nguyen
发明人： Baoson Nguyen
IPC分类号： H01L21336
CPC分类号： H01L29/7835
摘要： An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank having a surface is disposed within the well. The tank has a highly doped region of opposite conductivity type and a lightly doped region of opposite conductivity type between the highly doped region and the surface of tank. The lightly doped region in the tank is doped both the predetermined conductivity type and the opposite conductivity type with a resulting net lightly opposite conductivity type doping. A drain region of opposite conductivity type is disposed in the region of the tank between the highly doped region and the surface and disposed at the surface and a source region of opposite conductivity type is disposed in the well and spaced from the tank. The channel region includes the surface region of the tank between the drain region and the well and the surface region of the well between the source region and the tank, the junction region between the tank and the well having a graded doping level. The predetermined conductivity type is preferably p-type to provide an NMOS transistor.
摘要翻译：一种MOS器件和制造该器件的方法，该器件包括其中具有预定导电类型的阱的半导体衬底。具有表面的罐设置在井内。该槽具有相反导电类型的高度掺杂区域和在高掺杂区域和槽表面之间的相反导电类型的轻掺杂区域。罐中的轻掺杂区域掺杂了预定的导电类型和相反的导电类型，并产生了与之相反的导电型掺杂。具有相反导电类型的漏极区域设置在高掺杂区域和表面之间的槽区域中并且设置在表面处，并且具有相反导电类型的源极区域设置在阱中并与罐间隔开。通道区域包括在漏极区域和阱之间的槽的表面区域和源极区域和槽之间的阱的表面区域，罐和阱之间的结区域具有渐变的掺杂水平。预定的导电类型优选为p型以提供NMOS晶体管。

2. 发明授权

US5625278A Ultra-low drop-out monolithic voltage regulator 失效
标题翻译：超低压降单片式稳压器
公开(公告)号：US5625278A
公开(公告)日：1997-04-29
申请号：US623595
申请日：1996-03-28
申请人： Frank L. Thiel , Todd M. Neale , Baoson Nguyen , Fernando D. Carvajal
发明人： Frank L. Thiel , Todd M. Neale , Baoson Nguyen , Fernando D. Carvajal
IPC分类号： G05F1/575 , G05F1/40
CPC分类号： G05F1/575
摘要： The voltage regulator circuit contains a MOS transistor 12 connected between a voltage supply line 22 and an output line 30. The MOS transistor 12 provides a stable voltage on the output line 30 independent of voltage transients on the voltage supply line 22 and independent of current transients on the output line 30. An amplifier 14 coupled to the MOS transistor 12 controls the response of the MOS transistor 12. Feedback circuitry connected between the output line 30 and the amplifier 14 provides feedback to the amplifier 14. A voltage source 16 provides the reference for amplifier 14.
摘要翻译：电压调节器电路包括连接在电源线22和输出线30之间的MOS晶体管12.MOS晶体管12在输出线30上提供稳定的电压，而与电压供应线22上的电压瞬变无关，并且与电流瞬变无关耦合到MOS晶体管12的放大器14控制MOS晶体管12的响应。连接在输出线30和放大器14之间的反馈电路向放大器14提供反馈。电压源16提供参考用于放大器14。

3. 发明授权

US06639390B2 Protection circuit for miller compensated voltage regulators 有权
标题翻译：磨机补偿电压调节器的保护电路
公开(公告)号：US06639390B2
公开(公告)日：2003-10-28
申请号：US10113081
申请日：2002-04-01
申请人： Raul A. Perez , Baoson Nguyen
发明人： Raul A. Perez , Baoson Nguyen
IPC分类号： G05F140
CPC分类号： G05F1/565
摘要： A capacitively compensated voltage regulator, adapted to be supplied with power from a voltage supply, and having an input port and an output port. The voltage regulator includes a voltage regulation circuit responsive to a reference voltage at the input port to provide a regulated voltage at the output port, including a compensation capacitor having a plate connected to a node internal to the voltage regulator, and including a current source coupled between the voltage supply and the internal node. The voltage regulator also includes a low power control circuit responsive to a low power command signal. The low power control circuit includes a delay circuit responsive to a transition in the level of the low power command signal to generate a low power control signal for a predetermined time period after said transition, and also a bypass circuit coupled between the internal node and the voltage supply, responsive to the low power control signal to provide, for the predetermined time period, a current higher than the current provided by the current source, and otherwise to provide substantially no current. By the action of the standby control circuit a voltage overshoot or surge at the output port of the voltage regulator circuit is avoided.
摘要翻译：一种电容补偿电压调节器，适于从电源供应电力，并具有输入端口和输出端口。电压调节器包括响应于输入端口处的参考电压的电压调节电路，以在输出端口处提供调节电压，包括具有连接到电压调节器内部的节点的板的补偿电容器，并且包括电流源耦合在电源和内部节点之间。电压调节器还包括响应于低功率命令信号的低功率控制电路。低功率控制电路包括响应于低功率指令信号电平的转变的延迟电路，以在所述转换之后的预定时间段内产生低功率控制信号，以及耦合在内部节点和电压供应，响应于低功率控制信号，以在预定时间段内提供高于由电流源提供的电流的电流，否则基本上不提供电流。通过待机控制电路的动作，避免了电压调节器电路的输出端口的电压过冲或浪涌。

4. 发明授权

US06225796B1 Zero temperature coefficient bandgap reference circuit and method 有权
标题翻译：零温度系数带隙参考电路及方法
公开(公告)号：US06225796B1
公开(公告)日：2001-05-01
申请号：US09602164
申请日：2000-06-22
申请人： Baoson Nguyen
发明人： Baoson Nguyen
IPC分类号： G05F316
CPC分类号： G05F3/30
摘要： In one aspect, the present invention provides a method of generating a substantially constant voltage. A bandgap reference circuit (112/114/116) is trimmed such that a voltage output (VBG) from the bandgap reference circuit is at its peak value when an operating temperature is at its minimum value within a specified operating temperature range. A plurality of additional current sources (118-124) are also provided with the bandgap reference circuit. Each current source is designed to successively provide additional current as the operating temperature increases within the specified operating temperature range.
摘要翻译：一方面，本发明提供一种产生基本恒定电压的方法。修整带隙基准电路（112/114/116），使得当工作温度在指定工作温度范围内的最小值时，来自带隙基准电路的电压输出（VBG）处于其峰值。多个附加电流源（118-124）也带有带隙基准电路。每个电流源设计成在工作温度在指定的工作温度范围内增加时，依次提供额外的电流。

5. 发明授权

US06177829B1 Device for improving the switching efficiency of an integrated circuit charge pump 有权
标题翻译：用于提高集成电路电荷泵的开关效率的装置
公开(公告)号：US06177829B1
公开(公告)日：2001-01-23
申请号：US09196335
申请日：1998-11-19
申请人： Roy Clifton Jones, III , Wayne T. Chen , David Cotton , Baoson Nguyen
发明人： Roy Clifton Jones, III , Wayne T. Chen , David Cotton , Baoson Nguyen
IPC分类号： G05F302
CPC分类号： H02M3/073
摘要： A charge pump uses switching transistors including a PMOS transistor (P1), a first transistor (N1), and a second transistor (N2) instead of diodes (D1, D2) to control the transfer of charge from a pump capacitor (14) to a storage capacitor (20). The voltage (60) at the storage capacitor (20) is applied to a level shifter (13) and to the source of the PMOS transistor (P1) which, in turn, biases the first transistor (N1) during low state of an oscillating waveform (30B). A supply rail (140) charges the pump capacitor (14) when the first transistor (N1) is in its active region during the low state of the oscillating waveform (30B) and turns OFF during the high state of the waveform (30B) causing the charge on the pump capacitor (14) to be transferred to the storage capacitor (20). The level shifter (13) is used to synchronize the oscillating waveform (30B) so that no charge is lost from the pump capacitor (14) back to the supply and minimal charge is conducted through a parasitic diode (55).
摘要翻译：电荷泵使用包括PMOS晶体管（P1），第一晶体管（N1）和第二晶体管（N2）的开关晶体管代替二极管（D1，D2），以控制从泵浦电容器（14）到存储电容器（20）。在存储电容器（20）处的电压（60）被施加到电平移位器（13）和PMOS晶体管（P1）的源极，PMOS晶体管（P1）进而在低振荡状态期间偏置第一晶体管（N1）波形（30B）。当振荡波形（30B）的低状态期间第一晶体管（N1）处于其有源区域时，供电轨（140）对泵电容器（14）充电，并且在波形（30B）的高状态期间断开泵电容器（14）上的电荷被传送到存储电容器（20）。电平移位器（13）用于使振荡波形（30B）同步，使得没有电荷从泵浦电容器（14）流回电源，并且最小电荷通过寄生二极管（55）传导。

6. 发明授权

US07272523B1 Trimming for accurate reference voltage 有权
公开(公告)号：US07272523B1
公开(公告)日：2007-09-18
申请号：US11364741
申请日：2006-02-28
申请人： Soji K. John , Baoson Nguyen , Terry L. Mayhugh
发明人： Soji K. John , Baoson Nguyen , Terry L. Mayhugh
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/14
摘要： A method for trimming reference voltage circuitry includes defining a desired target reference voltage for a set of at least one die. At least two reference voltages are measured for at least two different trim settings associated with a given die of the at least one die. A modified target reference voltage is determined for the given die based on the at least two measured reference voltages. A trim setting associated with the reference voltage circuitry of the given die is set according to the modified target reference voltage so as to compensate for an offset voltage and substantially achieve the desired target reference voltage.

7. 发明授权

US5391980A Second order low temperature coefficient bandgap voltage supply 失效
标题翻译：二阶低温系数带隙电压供应
公开(公告)号：US5391980A
公开(公告)日：1995-02-21
申请号：US78705
申请日：1993-06-16
申请人： Frank L. Thiel , Baoson Nguyen
发明人： Frank L. Thiel , Baoson Nguyen
IPC分类号： G05F3/30
CPC分类号： G05F3/30 , Y10S323/907
摘要： A voltage reference circuit (2) is provided which includes a 2nd order curvature correction circuit (3) that eliminates undesirable 2nd order polynomial temperature dependency characteristics. A bandgap reference circuit (Q4, Q3, Q2, Q1, R2 and R1) forms a bandgap current (I.sub.X) that is dependent upon absolute temperature. A translinear cell (Q15, Q14, Q13, Q12, Q11 and Q10) transforms this current in a squaring transformation and divides the squared current by a temperature independent current (I.sub.X). A current mirror (Q17 and Q16) adjusts the value of the squared current so that it approximates the value of the 2nd order term of the bandgap reference circuit.
摘要翻译：提供了一种电压参考电路（2），其包括消除不期望的二阶多项式温度依赖特性的二阶曲率校正电路（3）。带隙参考电路（Q4，Q3，Q2，Q1，R2和R1）形成取决于绝对温度的带隙电流（IX）。跨平面电池（Q15，Q14，Q13，Q12，Q11和Q10）在平方变换中转换该电流，并将平方电流除以独立于温度的电流（IX）。电流镜（Q17和Q16）调整平方电流的值，使其近似于带隙基准电路的二阶项的值。

8. 发明授权

US5347210A Current switch with bipolar switching transistor and .beta. compensating circuit 失效
标题翻译：双极开关晶体管和β补偿电路的电流开关
公开(公告)号：US5347210A
公开(公告)日：1994-09-13
申请号：US40763
申请日：1993-03-31
申请人： Baoson Nguyen
发明人： Baoson Nguyen
IPC分类号： G05F3/22 , G05F3/16
CPC分类号： G05F3/22
摘要： A current switch (30) includes a switching transistor (Q1) having a collector electrode for coupling to a first voltage source (Vcc), an emitter electrode, and a base electrode for receiving a control signal (V.sub.IN1). Switching transistor (Q1) is responsive to the control signal (V.sub.IN1) to turn on to produce a collector current (I.sub.CQ1). A bias circuit (26) is coupled to the emitter electrode of the switching transistor (Q1) for causing the collector current (I.sub.CQ1) of the switching transistor (Q1) to have a predetermined value. The bias circuit includes first and second transistors (Q3 and Q4) having base electrodes coupled in common. The first transistor (Q3) has a collector electrode coupled to the emitter electrode of the switching transistor (Q1) and an emitter electrode for coupling to a second voltage source (Vss). The second transistor has a collector electrode for coupling to a current source (24) and an emitter electrode for coupling to the second voltage source (Vss). A third transistor (Q6) has a collector electrode coupled to the emitter electrode of the switching transistor (Q1), a emitter electrode coupled to the base electrode of the first transistor (Q3), and a control electrode coupled to the collector electrode of the second transistor (Q4). The third transistor (Q6) reduces the dependance of the collector current (I.sub.CQ1) on the .beta. of the switching transistor (Q1) to make the collector current (I.sub.CQ1) less sensitive to process variations.
摘要翻译：电流开关（30）包括具有用于耦合到第一电压源（Vcc）的集电极的开关晶体管（Q1），用于接收控制信号（VIN1）的发射极和基极。开关晶体管（Q1）响应于控制信号（VIN1）导通以产生集电极电流（ICQ1）。偏置电路（26）耦合到开关晶体管（Q1）的发射极，以使开关晶体管（Q1）的集电极电流（ICQ1）具有预定值。偏置电路包括具有共同连接的基极的第一和第二晶体管（Q3和Q4）。第一晶体管（Q3）具有耦合到开关晶体管（Q1）的发射极的集电极和用于耦合到第二电压源（Vss）的发射极。第二晶体管具有用于耦合到电流源（24）的集电极和用于耦合到第二电压源（Vss）的发射极。第三晶体管（Q6）具有耦合到开关晶体管（Q1）的发射极的集电极，耦合到第一晶体管（Q3）的基极的发射极，以及耦合到第一晶体管第二晶体管（Q4）。第三晶体管（Q6）降低了集电极电流（ICQ1）对开关晶体管（Q1）的β的依赖性，使集电极电流（ICQ1）对工艺变化不太敏感。

9. 发明申请

US20070203661A1 Trimming for accurate reference voltage 有权
标题翻译：修整精确的参考电压
公开(公告)号：US20070203661A1
公开(公告)日：2007-08-30
申请号：US11364741
申请日：2006-02-28
申请人： Soji John , Baoson Nguyen , Terry Mayhugh
发明人： Soji John , Baoson Nguyen , Terry Mayhugh
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L22/14
摘要： A method for trimming reference voltage circuitry includes defining a desired target reference voltage for a set of at least one die. At least two reference voltages are measured for at least two different trim settings associated with a given die of the at least one die. A modified target reference voltage is determined for the given die based on the at least two measured reference voltages. A trim setting associated with the reference voltage circuitry of the given die is set according to the modified target reference voltage so as to compensate for an offset voltage and substantially achieve the desired target reference voltage.
摘要翻译：用于修整参考电压电路的方法包括为一组至少一个管芯定义所需的目标参考电压。对于与至少一个管芯的给定管芯相关联的至少两个不同的修整设置来测量至少两个参考电压。基于至少两个测量的参考电压，为给定的管芯确定修改的目标参考电压。根据修改的目标参考电压来设置与给定裸片的参考电压电路相关联的微调设置，以补偿偏移电压并基本上实现期望的目标参考电压。

10. 发明授权

US06172406B2 Breakdown drain extended NMOS 有权
标题翻译：击穿漏极扩展NMOS
公开(公告)号：US06172406B2
公开(公告)日：2001-01-09
申请号：US09140254
申请日：1998-08-26
申请人： Baoson Nguyen
发明人： Baoson Nguyen
IPC分类号： H01L31119
CPC分类号： H01L29/7835
摘要： An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank having a surface is disposed within the well. The tank has a highly doped region of opposite conductivity type and a lightly doped region of opposite conductivity type between the highly doped region and the surface of tank. The lightly doped region in the tank is doped both the predetermined conductivity type and the opposite conductivity type with a resulting net lightly opposite conductivity type doping. A drain region of opposite conductivity type is disposed in the region of the tank between the highly doped region and the surface and disposed at the surface and a source region of opposite conductivity type is disposed in the well and spaced from the tank. The channel region includes the surface region of the tank between the drain region and the well and the surface region of the well between the source region and the tank, the junction region between the tank and the well having a graded doping level. The predetermined conductivity type is preferably p-type to provide an NMOS transistor.
摘要翻译：一种MOS器件和制造该器件的方法，该器件包括其中具有预定导电类型的阱的半导体衬底。具有表面的罐设置在井内。该槽具有相反导电类型的高度掺杂区域和在高掺杂区域和槽表面之间的相反导电类型的轻掺杂区域。罐中的轻掺杂区域掺杂了预定的导电类型和相反的导电类型，并产生了与之相反的导电型掺杂。具有相反导电类型的漏极区域设置在高掺杂区域和表面之间的槽区域中并且设置在表面处，并且具有相反导电类型的源极区域设置在阱中并与罐间隔开。通道区域包括在漏极区域和阱之间的槽的表面区域和源极区域和槽之间的阱的表面区域，罐和阱之间的结区域具有渐变的掺杂水平。预定的导电类型优选为p型以提供NMOS晶体管。

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