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    • 8. 发明授权
    • Flexible on chip testing circuit for I/O's characterization
    • 用于I / O表征的灵活的片上测试电路
    • US07772833B2
    • 2010-08-10
    • US12135418
    • 2008-06-09
    • Narayanan VijayaraghavanBalwant Singh
    • Narayanan VijayaraghavanBalwant Singh
    • G01R31/28
    • G01R31/31715
    • The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.
    • 本发明提供了用于测量多个I / O结构的I / O表征的灵活的片上测试电路和方法。 测试电路包括寄存器组,中央处理控制器(CPC),字符转换模块,延迟表征模块和字符频率模块。 注册银行存储多个指令和测量结果。 CPC从注册银行取得指示。 CPC包括用于解释获取的指令执行的各种主要和次要状态机。 根据输入指令,CPC对IUT应用激励,IUT的输出由本地表征模块(CHARMODULE)用于提取所需的特性参数,例如测量电压上升/下降时间的字符转换模块, 单电压IUT或多电压IUT。 STIOBISC的测试方法包括通过将ATE数据日志转换为最终可读格式的验证测试台和自动化结果处理的自动ATE模式生成,从而大大降低了测试设置和输出处理时间。 测试电路可以在多种模式下工作,以选择这些模块之一。
    • 9. 发明授权
    • Resolution in measuring the pulse width of digital signals
    • 分辨率测量数字信号的脉冲宽度
    • US07516032B2
    • 2009-04-07
    • US10327705
    • 2002-12-20
    • Balwant Singh
    • Balwant Singh
    • G06F19/00G01R29/02G01R25/08
    • G01R31/2882G01R29/02G01R31/3016G01R31/31937
    • A system and method for providing improved resolution in the measuring the pulse width of digital signals comprising counting the integral number of measuring clock pulses covered by said digital pulse and triggering a chain of cascaded high resolution delay elements from the trailing edge of said measuring clock pulses. Further, the invention measures the delay count obtained from said chain of cascaded delay elements from the trailing edge of the last measuring clock pulse up to the end of said digital pulse, and adds said measured delay count to said integral measuring clock pulse count to obtain the total width of said digital pulse.
    • 一种用于在测量数字信号的脉冲宽度时提供改进的分辨率的系统和方法,包括对由所述数字脉冲覆盖的测量时钟脉冲的整数进行计数,并从所述测量时钟脉冲的后沿触发级联的高分辨率延迟元件链 。 此外,本发明还测量从所述最后测量时钟脉冲的后沿到所述数字脉冲的末端从所述级联延迟元件链获得的延迟计数,并将所述测量的延迟计数加到所述积分测量时钟脉冲计数以获得 所述数字脉冲的总宽度。