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1. 发明申请

US20080231310A1 FLEXIBLE ON CHIP TESTING CIRCUIT FOR I/O'S CHARACTERIZATION 审中-公开
标题翻译：芯片测试电路灵活的I / O特性
公开(公告)号：US20080231310A1
公开(公告)日：2008-09-25
申请号：US11875837
申请日：2007-10-20
申请人： Narayanan Vijayaraghavan , Balwant Singh
发明人： Narayanan Vijayaraghavan , Balwant Singh
IPC分类号： G01R31/26
CPC分类号： G01R31/31715
摘要： The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.
摘要翻译：本发明提供了用于测量多个I / O结构的I / O表征的灵活的片上测试电路和方法。测试电路包括寄存器组，中央处理控制器（CPC），字符转换模块，延迟表征模块和字符频率模块。注册银行存储多个指令和测量结果。 CPC从注册银行取得指示。 CPC包括用于解释获取的指令执行的各种主要和次要状态机。根据输入指令，CPC对IUT应用激励，IUT的输出由本地表征模块（CHARMODULE）用于提取所需的特性参数，例如测量电压上升/下降时间的字符转换模块，单电压IUT或多电压IUT。 STIOBISC的测试方法包括通过将ATE数据日志转换为最终可读格式的验证测试台和自动化结果处理的自动ATE模式生成，从而大大降低了测试设置和输出处理时间。测试电路可以在多种模式下工作，以选择这些模块之一。

2. 发明授权

US07772833B2 Flexible on chip testing circuit for I/O's characterization 有权
标题翻译：用于I / O表征的灵活的片上测试电路
公开(公告)号：US07772833B2
公开(公告)日：2010-08-10
申请号：US12135418
申请日：2008-06-09
申请人： Narayanan Vijayaraghavan , Balwant Singh
发明人： Narayanan Vijayaraghavan , Balwant Singh
IPC分类号： G01R31/28
CPC分类号： G01R31/31715
摘要： The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.
摘要翻译：本发明提供了用于测量多个I / O结构的I / O表征的灵活的片上测试电路和方法。测试电路包括寄存器组，中央处理控制器（CPC），字符转换模块，延迟表征模块和字符频率模块。注册银行存储多个指令和测量结果。 CPC从注册银行取得指示。 CPC包括用于解释获取的指令执行的各种主要和次要状态机。根据输入指令，CPC对IUT应用激励，IUT的输出由本地表征模块（CHARMODULE）用于提取所需的特性参数，例如测量电压上升/下降时间的字符转换模块，单电压IUT或多电压IUT。 STIOBISC的测试方法包括通过将ATE数据日志转换为最终可读格式的验证测试台和自动化结果处理的自动ATE模式生成，从而大大降低了测试设置和输出处理时间。测试电路可以在多种模式下工作，以选择这些模块之一。

3. 发明申请

US20090076753A1 FLEXIBLE ON CHIP TESTING CIRCUIT FOR I/O'S CHARACTERIZATION 有权
标题翻译：芯片测试电路灵活的I / O特性
公开(公告)号：US20090076753A1
公开(公告)日：2009-03-19
申请号：US12135418
申请日：2008-06-09
申请人： Narayanan Vijayaraghavan , Balwant Singh
发明人： Narayanan Vijayaraghavan , Balwant Singh
IPC分类号： G01R31/317
CPC分类号： G01R31/31715
摘要： The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.
摘要翻译：本发明提供了用于测量多个I / O结构的I / O表征的灵活的片上测试电路和方法。测试电路包括寄存器组，中央处理控制器（CPC），字符转换模块，延迟表征模块和字符频率模块。注册银行存储多个指令和测量结果。 CPC从注册银行取得指示。 CPC包括用于解释获取的指令执行的各种主要和次要状态机。根据输入指令，CPC对IUT应用激励，IUT的输出由本地表征模块（CHARMODULE）用于提取所需的特性参数，例如测量电压上升/下降时间的字符转换模块，单电压IUT或多电压IUT。 STIOBISC的测试方法包括通过将ATE数据日志转换为最终可读格式的验证测试台和自动化结果处理的自动ATE模式生成，从而大大降低了测试设置和输出处理时间。测试电路可以在多种模式下工作，以选择这些模块之一。

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