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    • 6. 发明授权
    • Method, network element and system for scheduling communication link
    • 方法,网元和系统调度通信链路
    • US09100980B2
    • 2015-08-04
    • US13583264
    • 2010-03-08
    • Yi WuHai Jiang
    • Yi WuHai Jiang
    • H04W72/12H04B7/26
    • H04W72/1263H04B7/2656H04W72/1257
    • Provided is a method for scheduling a communication link, wherein the communication link is adapted for connecting two network elements, wherein a first carrier and a second carrier are assigned to the communication link, wherein each carrier includes frames divided into timeslots, and a predefined number of timeslots is allocated for downlink communication and a predefined number of timeslots is allocated for uplink communication. The method includes scheduling the communication link for offsetting the start of the frames of the first carrier in respect to the start of the frames of the second carrier. Also provided are a network element adapted for carrying out the method and a system including the network element.
    • 提供了一种用于调度通信链路的方法,其中通信链路适于连接两个网络元件,其中第一载波和第二载波被分配给通信链路,其中每个载波包括划分为时隙的帧和预定义的数字 分配时隙用于下行链路通信,并且预定数量的时隙被分配用于上行链路通信。 该方法包括调度通信链路,以相对于第二载波的帧的开始来抵消第一载波的帧的开始。 还提供了适于执行该方法的网元和包括该网元的系统。
    • 9. 发明授权
    • Routing nets over circuit blocks in a hierarchical circuit design
    • 在分层电路设计中的路由网络过电路块
    • US08255855B2
    • 2012-08-28
    • US12490023
    • 2009-06-23
    • Yi WuDajen HuangKalon S. Holdbrook
    • Yi WuDajen HuangKalon S. Holdbrook
    • G06F17/50
    • G06F17/5077
    • Some embodiments of the present invention provide a system that routes nets over circuit blocks in a hierarchical circuit design. During operation, the system can receive a set of circuit blocks. At least some terminals of the circuit blocks may be desired to be electrically linked together using a net which is expected to be routed over one or more circuit blocks. The system may divide an area associated with a block (e.g., an area in a metal layer which is situated above the block) into a set of tiles. Next, the system may assign costs to at least some of the tiles in the set of tiles. The system can then use the costs during routing. Note that using the costs of the tiles during routing makes it more likely that buffers can be used wherever required to meet slew and timing requirements.
    • 本发明的一些实施例提供一种在分层电路设计中将网络路由到电路块上的系统。 在运行期间,系统可以接收一组电路块。 电路块的至少一些端子可能期望使用期望在一个或多个电路块上布线的网电连接在一起。 系统可以将与块(例如,位于块之上的金属层中的区域)相关联的区域划分成一组瓦片。 接下来,系统可以将成本分配给该组瓦片中的至少一些瓦片。 然后,系统可以在路由期间使用成本。 请注意,在路由期间使用瓦片的成本使得缓冲区更有可能在需要满足压缩和时序要求的地方使用。
    • 10. 发明授权
    • Via antenna fix in deep sub-micron circuit designs
    • 通过天线固定在深亚微米电路设计中
    • US07994543B2
    • 2011-08-09
    • US11828515
    • 2007-07-26
    • Yi WuKenan Yu
    • Yi WuKenan Yu
    • H01L27/10H01L29/73
    • H01L27/0629H01L27/0255
    • A filler cell for use in fabricating an integrated circuit. The filler cell couples a power supply rail of an adjacent logic cell to a power supply rail of another adjacent logic cell. The filler cell also has a diode to bleed charge accumulated on the power rails of the adjacent logic cells to the substrate. The diode is reverse biased during normal integrated circuit operation. A method for fabricating an integrated circuit with a power grid. At least one filler cell is placed on the integrated circuit to bleed away charge accumulated on the power grid during the fabrication of the integrated circuit. The filler cell is connected to a supply rail of an adjacent logic cell.
    • 一种用于制造集成电路的填充电池。 填充单元将相邻逻辑单元的电源轨耦合到另一相邻逻辑单元的电源轨。 填充单元还具有二极管,以将积聚在相邻逻辑单元的电源轨上的电荷泄放到衬底。 在正常集成电路操作期间,二极管反向偏置。 一种用电网制造集成电路的方法。 在集成电路的制造期间,至少一个填充单元被放置在集成电路上以排除积聚在电网上的电荷。 填充单元连接到相邻逻辑单元的电源轨。