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1. 发明申请

US20070158781A1 ELECTRICAL FUSES COMPRISING THIN FILM TRANSISTORS (TFTS), AND METHODS FOR PROGRAMMING SAME 有权
标题翻译：包含薄膜晶体管（TFTS）的电熔丝及其编程方法
公开(公告)号：US20070158781A1
公开(公告)日：2007-07-12
申请号：US11306597
申请日：2006-01-04
申请人： Babar Khan , Chandrasekharan Kothandaraman , Kai Xiu
发明人： Babar Khan , Chandrasekharan Kothandaraman , Kai Xiu
IPC分类号： H01L29/00
CPC分类号： H01L29/42384 , H01L23/345 , H01L23/5256 , H01L29/78669 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to electrical fuses that each comprises at least one thin film transistor. In one embodiment, the electrical fuse of the present invention comprises a hydrogenated thin film transistor with an adjacent heating element. Programming of such an electrical fuse can be effectuated by heating the hydrogenated thin film transistor so as to cause at least partial dehydrogenation. Consequentially, the thin film transistor exhibits detectible physical property change(s), which defines a programmed state. In an alternative embodiment of the present invention, the electrical fuse comprises a thin film transistor that is either hydrogenated or not hydrogenated. Programming of such an alternative electrical fuse can be effectuated by applying a sufficient high back gate voltage to the thin film transistor to cause state changes in the channel-gate interface. In this manner, the thin film transistor also exhibits detectible property change(s) to define a programmed state.
摘要翻译：本发明涉及电熔丝，每个电熔丝包括至少一个薄膜晶体管。在一个实施例中，本发明的电熔丝包括具有相邻加热元件的氢化薄膜晶体管。可以通过加热氢化薄膜晶体管来实现这种电熔丝的编程，从而至少部分脱氢。因此，薄膜晶体管表现出可检测的物理特性变化，其定义了编程状态。在本发明的替代实施例中，电熔丝包括被氢化或未氢化的薄膜晶体管。可以通过向薄膜晶体管施加足够的高背栅电压来引起通道栅极界面的状态变化来实现这种替代电熔丝的编程。以这种方式，薄膜晶体管还具有可检测的特性变化以限定编程状态。

2. 发明授权

US5237436A Active matrix electro-optic display device with light shielding layer and projection and color employing same 失效
标题翻译：主动矩阵电光显示装置，具有遮光层，投影和采用相同的颜色
公开(公告)号：US5237436A
公开(公告)日：1993-08-17
申请号：US899154
申请日：1992-06-12
申请人： Babar Khan , Edward H. Stupp , Mali Venkatesan
发明人： Babar Khan , Edward H. Stupp , Mali Venkatesan
IPC分类号： G02F1/1362
CPC分类号： G02F1/136209
摘要： The thin film switch of a pixel of an active matrix liquid crystal light valve is shielded from light by adding a light shielding layer of amorphous germanium or germaniums nitride in the interpixel area surrounding the pixel electrodes. Such active matrix displays are advantageously employed in a color projection TV to produce the separate red, blue and green components of a full color display.
摘要翻译：通过在围绕像素电极的像素间区域中添加无定形锗或氮化锗的遮光层，有源矩阵液晶光阀的像素的薄膜开关被遮光。这样的有源矩阵显示器有利地用于彩色投影电视中，以产生全色显示器的分开的红色，蓝色和绿色分量。

3. 发明申请

US20060160298A1 SELF-ALIGNED, SILICIDED, TRENCH-BASED, DRAM/EDRAM PROCESSES WITH IMPROVED RETENTION 有权
标题翻译：自对准，硅胶，基于TRENCH，具有改进保持性的DRAM / EDRAM工艺
公开(公告)号：US20060160298A1
公开(公告)日：2006-07-20
申请号：US10905684
申请日：2005-01-17
申请人： Oh-Jung Kwon , Kim Bosang , Herbert Ho , Babar Khan , Deok-kee Kim
发明人： Oh-Jung Kwon , Kim Bosang , Herbert Ho , Babar Khan , Deok-kee Kim
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10867 , H01L27/10888
摘要： A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.
摘要翻译：衬底中的DRAM单元具有从衬底的表面延伸到衬底中的深沟槽（DT），形成在与深沟槽相邻的衬底的表面上的字线（WL）和设置在衬底中的氧化物（TTO）沟槽的顶部并且在字线的方向上延伸超过沟槽。以这种方式，当硅化时，在位于深沟槽之上的字线（WL）和通过字线（PWL）之间的间隙中，衬底表面上存在氧化物而不是硅。

4. 发明申请

US20170127683A1 BIOFILM PREVENTION, DISRUPTION AND TREATMENT WITH BACTERIOPHAGE LYSIN 审中-公开
公开(公告)号：US20170127683A1
公开(公告)日：2017-05-11
申请号：US15293586
申请日：2016-10-14
申请人： Raymond Schuch , Robert C. Nowinski , Michael Wittekind , Babar Khan , Jimmy Rotolo
发明人： Raymond Schuch , Robert C. Nowinski , Michael Wittekind , Babar Khan , Jimmy Rotolo
IPC分类号： A01N63/00 , A61K45/06 , A61K38/47
CPC分类号： A01N63/00 , A61K38/16 , A61K38/164 , A61K38/47 , A61K45/06 , A61L29/08 , A61L29/16 , A61L2300/404 , A61L2300/406 , A61L2420/00 , C07K14/315 , C12N9/503 , C12Y302/01017
摘要： The present invention provides methods for the prevention, control, disruption and treatment of bacterial biofilms with lysin, particularly lysin having capability to kill Staphylococcal bacteria, including drug resistant Staphylococcus aureus, particularly the lysin PlySs2. The invention also provides compositions and methods for use in treatment or modulation of bacterial biofilm(s) and biofilm formation.

5. 发明申请

US20070257294A1 DRAM (DYNAMIC RANDOM ACCESS MEMORY) CELLS 失效
公开(公告)号：US20070257294A1
公开(公告)日：2007-11-08
申请号：US11780022
申请日：2007-07-19
申请人： Kangguo Cheng , Babar Khan
发明人： Kangguo Cheng , Babar Khan
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/1087
摘要： A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, but electrically insulated from the first portion by a capacitor dielectric layer; (d) a second doped semiconductor region wrapping around the second portion, but electrically insulated from the second portion by a collar dielectric layer. The second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion. The collar dielectric layer is in direct physical contact with the capacitor dielectric layer. When going away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.

6. 发明申请

US20060118850A1 COLLARLESS TRENCH DRAM DEVICE 失效
标题翻译：无缝TRENCH DRAM设备
公开(公告)号：US20060118850A1
公开(公告)日：2006-06-08
申请号：US10904933
申请日：2004-12-06
申请人： Yoichi Otani , Herbert Ho , Babar Khan , Paul Parries
发明人： Yoichi Otani , Herbert Ho , Babar Khan , Paul Parries
IPC分类号： H01L29/76 , H01L21/20
CPC分类号： H01L29/945 , H01L27/1087
摘要： The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same.
摘要翻译：本发明提供了具有最小化的垂直寄生FET泄漏的无凹槽沟槽半导体存储器件及其形成方法。

7. 发明授权

US06703312B2 Method of forming active devices of different gatelengths using lithographic printed gate images of same length 失效
标题翻译：使用相同长度的平版印刷门图像形成不同长度的有源器件的方法
公开(公告)号：US06703312B2
公开(公告)日：2004-03-09
申请号：US10151074
申请日：2002-05-17
申请人： John Walter Golz , Babar Khan , Joyce C. Liu , Christopher Joseph Waskiewicz , Teresa Jacqueline Wu
发明人： John Walter Golz , Babar Khan , Joyce C. Liu , Christopher Joseph Waskiewicz , Teresa Jacqueline Wu
IPC分类号： H01L21301
CPC分类号： H01L21/823468 , H01L21/823456
摘要： As disclosed herein, a method is provided for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in a second portion such as an array portion of an integrated circuit. The method includes depositing a feature layer over a substrate and a hardmask material layer thereover. Photoresist patterns are then formed in the first and second portions with a critical dimension mask, and are then used to etch the hardmask material layer into hardmask patterns. Sidewall spacers are provided on sidewalls of the hardmask patterns in the second portion. Then, the feature layer is simultaneously etched in both first and second portions, using the hardmask patterns in the first portion to define features having a first width, and using the hardmask patterns and the sidewall spacers in the second portion to define features having a second width.
摘要翻译：如本文所公开的，提供了一种用于在诸如集成电路的逻辑部分的第一部分中同时构图具有第一宽度的特征的方法，并且在诸如集成电路的阵列部分的第二部分中具有第二宽度。该方法包括在基底上沉积特征层，并在其上沉积硬掩模材料层。然后用临界尺寸掩模在第一和第二部分中形成光致抗蚀剂图案，然后用于将硬掩模材料层蚀刻成硬掩模图案。侧壁间隔件设置在第二部分中的硬掩模图案的侧壁上。然后，使用第一部分中的硬掩模图案同时在第一和第二部分中蚀刻特征层，以限定具有第一宽度的特征，以及使用第二部分中的硬掩模图案和侧壁间隔物来限定具有第二部分的特征宽度。

8. 发明授权

US06410399B1 Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization 失效
标题翻译：通过硅化法降低基于沟槽的DRAMS中的带，字线和位线接触电阻的工艺
公开(公告)号：US06410399B1
公开(公告)日：2002-06-25
申请号：US09606493
申请日：2000-06-29
申请人： Philip Lee Flaitz , Herbert L. Ho , Subramanian Iyer , Babar Khan , Paul C. Parries
发明人： Philip Lee Flaitz , Herbert L. Ho , Subramanian Iyer , Babar Khan , Paul C. Parries
IPC分类号： H01L2120
CPC分类号： H01L27/10867 , H01L21/28052 , H01L21/28518 , H01L21/76895 , H01L29/665
摘要： A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.
摘要翻译：一种半导体器件制造方法，用于在动态随机存取存储器（DRAMS）和嵌入式DRAM（eDRAM）器件的阵列区域中硅化硅含量区域，以降低电阻，并在低温下提高器件的可靠性。

9. 发明授权

US5250444A Rapid plasma hydrogenation process for polysilicon MOSFETs 失效
标题翻译：多晶硅MOSFET的快速等离子体加氢工艺
公开(公告)号：US5250444A
公开(公告)日：1993-10-05
申请号：US842854
申请日：1992-02-21
申请人： Babar Khan , Barbara A. Rossi , Uday Mitra
发明人： Babar Khan , Barbara A. Rossi , Uday Mitra
IPC分类号： H01L21/31 , H01L21/30 , H01L21/324 , H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L21/3003 , Y10S148/128
摘要： A method for rapid plasma hydrogenation of semiconductor devices is provided in which the hydrogenation is conducted in two steps, the first step being conducted at a hydrogenation temperature that is higher than the out-diffusion temperature at which a substantial amount of hydrogen diffuses out of said semiconductor device; and in the second step, the semiconductor device is cooled to a temperature at which out-diffusion is substantially avoided while the hydrogenation plasma is maintained.

10. 发明申请

US20070235792A1 SELF-ALIGNED, SILICIDED, TRENCH-BASED DRAM/eDRAM PROCESSES WITH IMPROVED RETENTION 失效
标题翻译：自对准，硅胶，基于TRENCH的DRAM / eDRAM工艺具有改进的保留
公开(公告)号：US20070235792A1
公开(公告)日：2007-10-11
申请号：US11566360
申请日：2006-12-04
申请人： Oh-Jung Kwon , Kim Bosang , Herbert Ho , Babar Khan , Deok-kee Kim
发明人： Oh-Jung Kwon , Kim Bosang , Herbert Ho , Babar Khan , Deok-kee Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/10867 , H01L27/10888
摘要： A DRAM cell in a substrate has a deep trench (DT) extending from a surface of the substrate into the substrate, a word line (WL) formed on the surface of the substrate adjacent the deep trench, and oxide (TTO) disposed in a top portion of the trench and extending beyond the trench in the direction of the word line. In this manner, when silicided, there is oxide rather than silicon on the surface of the substrate in a gap between the word line (WL) and a passing word line (PWL) disposed above the deep trench.
摘要翻译：衬底中的DRAM单元具有从衬底的表面延伸到衬底中的深沟槽（DT），形成在与深沟槽相邻的衬底的表面上的字线（WL）和设置在衬底中的氧化物（TTO）沟槽的顶部并且在字线的方向上延伸超过沟槽。以这种方式，当硅化时，在位于深沟槽之上的字线（WL）和通过字线（PWL）之间的间隙中，衬底表面上存在氧化物而不是硅。

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