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1. 发明授权

US08539311B2 System and method for data recovery in multi-level cell memories 有权
标题翻译：用于多级单元存储器中的数据恢复的系统和方法
公开(公告)号：US08539311B2
公开(公告)日：2013-09-17
申请号：US13117008
申请日：2011-05-26
申请人： Avi Steiner , Michael Katz , Hanan Weingarten , Erez Sabbag , Ofir Avraham Kanter , Avigdor Segal
发明人： Avi Steiner , Michael Katz , Hanan Weingarten , Erez Sabbag , Ofir Avraham Kanter , Avigdor Segal
IPC分类号： G11C29/00
CPC分类号： G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3404
摘要： A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level.
摘要翻译：提供了一种用于多级单元存储器件中的数据恢复的系统和方法。可以在存储器件中的多级单元的一个或多个相应级别中顺序编程一个或多个位。可以检测到在多级单元的后续第二级或更高级别中编程后续位的中断。可以从定义在第二或更高级别的编程中断之前编程的一个或多个位的多级单元恢复数据。

2. 发明申请

US20120005558A1 SYSTEM AND METHOD FOR DATA RECOVERY IN MULTI-LEVEL CELL MEMORIES 有权
标题翻译：用于数据恢复在多层细胞记忆中的系统和方法
公开(公告)号：US20120005558A1
公开(公告)日：2012-01-05
申请号：US13117008
申请日：2011-05-26
申请人： Avi STEINER , Michael Katz , Hanan Weingarten , Erez Sabbag , Ofir Avraham Kanter , Avigdor Segal
发明人： Avi STEINER , Michael Katz , Hanan Weingarten , Erez Sabbag , Ofir Avraham Kanter , Avigdor Segal
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3404
摘要： A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level.
摘要翻译：提供了一种用于多级单元存储器件中的数据恢复的系统和方法。可以在存储器件中的多级单元的一个或多个相应级别中顺序编程一个或多个位。可以检测到在多级单元的后续第二级或更高级别中编程后续位的中断。可以从定义在第二或更高级别的编程中断之前编程的一个或多个位的多级单元恢复数据。

3. 发明授权

US08510639B2 System and method for multi-dimensional encoding and decoding 有权
标题翻译：用于多维编码和解码的系统和方法
公开(公告)号：US08510639B2
公开(公告)日：2013-08-13
申请号：US13171215
申请日：2011-06-28
申请人： Avi Steiner , Erez Sabbag , Avigdor Segal , Ilan Bar , Eli Sterin
发明人： Avi Steiner , Erez Sabbag , Avigdor Segal , Ilan Bar , Eli Sterin
IPC分类号： H03M13/00
CPC分类号： G06F11/10 , H03M13/09 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/2918 , H03M13/2927 , H03M13/293 , H03M13/2945 , H03M13/2948 , H03M13/2957 , H03M13/43 , H03M13/6561
摘要： A system and method for decoding multi-dimensional encoded data. A set of multi-dimensional encoded data may be received encoding each input bit in a set of input bits by multiple different component codes in multiple different encoding dimensions. The multi-dimensional data may potentially have errors. A map may be used to locate each set of intersection bits that encode the same input bit by multiple unsolved component codes. The unsolved component codes may be decoded using one or a plurality of tested error correction hypotheses that yields a decoding success, where each hypothesis correcting a different set of intersection bits for a different input bit. The successful hypothesis may be applied for correcting the multi-dimensional encoded data.
摘要翻译：一种用于解码多维编码数据的系统和方法。可以接收一组多维编码数据，该编码数据在多个不同编码维度中通过多个不同分量代码对一组输入比特中的每个输入比特进行编码。多维数据可能存在错误。可以使用映射来定位通过多个未解析分量代码编码相同输入比特的每个交集比特集合。可以使用产生解码成功的一个或多个测试的纠错假设来解码未解码的分量代码，其中每个假设校正不同输入比特的不同的交集比特。成功的假设可以应用于校正多维编码数据。

4. 发明授权

US08468431B2 System and method for multi-dimensional encoding and decoding 有权
标题翻译：用于多维编码和解码的系统和方法
公开(公告)号：US08468431B2
公开(公告)日：2013-06-18
申请号：US13171211
申请日：2011-06-28
申请人： Avi Steiner , Erez Sabbag , Avigdor Segal , Ilan Bar , Eli Sterin
发明人： Avi Steiner , Erez Sabbag , Avigdor Segal , Ilan Bar , Eli Sterin
IPC分类号： H03M13/00
CPC分类号： G06F11/10 , H03M13/09 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/2918 , H03M13/2927 , H03M13/293 , H03M13/2945 , H03M13/2948 , H03M13/2957 , H03M13/43 , H03M13/6561
摘要： A system and method is provided for decoding a set of bits using a plurality of hypotheses, for example, each independently tested on-the-fly. Initial bit states and associated reliability metrics may be received for the set of bits. A current hypothesis may be decoded for correcting the set of bits, wherein the current hypothesis defines different bit states and associated reliability metrics for the set of bits. If decoding the current hypothesis is not successful, a subsequently ordered hypothesis may be decoded, wherein the hypotheses are ordered such that their associated reliability metric is a monotonically non-decreasing sequence. Decoding may proceed iteratively until the current hypothesis is successful.
摘要翻译：提供了一种用于使用多个假设对一组位进行解码的系统和方法，例如，每个假设都在运行中独立测试。可以针对该组位接收初始位状态和相关的可靠性度量。可以解码当前假设以校正该组比特，其中当前假设定义了该组比特的不同比特状态和相关联的可靠性度量。如果对当前假设的解码不成功，则可以解码随后排序的假设，其中假设被排序使得其相关联的可靠性度量是单调非递减序列。解码可以迭代地进行，直到当前假设成功。

5. 发明授权

US08621321B2 System and method for multi-dimensional encoding and decoding 有权
标题翻译：用于多维编码和解码的系统和方法
公开(公告)号：US08621321B2
公开(公告)日：2013-12-31
申请号：US13171214
申请日：2011-06-28
申请人： Avi Steiner , Erez Sabbag , Avigdor Segal , Ilan Bar , Eli Sterin
发明人： Avi Steiner , Erez Sabbag , Avigdor Segal , Ilan Bar , Eli Sterin
IPC分类号： H03M13/00
CPC分类号： G06F11/10 , H03M13/09 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/2918 , H03M13/2927 , H03M13/293 , H03M13/2945 , H03M13/2948 , H03M13/2957 , H03M13/43 , H03M13/6561
摘要： A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.
摘要翻译：一种使用循环冗余校验（CRC）来评估误差校正的系统和方法。可以接收与其相关联的一组数据和初始CRC值。可以校正通过改变数据的子集的数据集。可以与所述校正并行地为整个未校正的数据集计算中间CRC值。可以在所述校正之后仅对改变的数据的子集计算补充CRC值。可以组合中间和补充CRC值以产生用于整个校正数据集的CRC值。可以通过将组合的CRC值与初始CRC值进行比较来评估校正的数据集合的有效性。

6. 发明申请

US20120005560A1 SYSTEM AND METHOD FOR MULTI-DIMENSIONAL ENCODING AND DECODING 有权
标题翻译：用于多维编码和解码的系统和方法
公开(公告)号：US20120005560A1
公开(公告)日：2012-01-05
申请号：US13171211
申请日：2011-06-28
申请人： Avi STEINER , Erez SABBAG , Avigdor Segal , Ilan Bar , Eli Sterin
发明人： Avi STEINER , Erez SABBAG , Avigdor Segal , Ilan Bar , Eli Sterin
IPC分类号： H03M13/45 , G06F11/10
CPC分类号： G06F11/10 , H03M13/09 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/2918 , H03M13/2927 , H03M13/293 , H03M13/2945 , H03M13/2948 , H03M13/2957 , H03M13/43 , H03M13/6561
摘要： A system and method is provided for decoding a set of bits using a plurality of hypotheses, for example, each independently tested on-the-fly. Initial bit states and associated reliability metrics may be received for the set of bits. A current hypothesis may be decoded for correcting the set of bits, wherein the current hypothesis defines different bit states and associated reliability metrics for the set of bits. If decoding the current hypothesis is not successful, a subsequently ordered hypothesis may be decoded, wherein the hypotheses are ordered such that their associated reliability metric is a monotonically non-decreasing sequence. Decoding may proceed iteratively until the current hypothesis is successful.
摘要翻译：提供了一种用于使用多个假设对一组位进行解码的系统和方法，例如，每个假设都在运行中独立测试。可以针对该组位接收初始位状态和相关的可靠性度量。可以解码当前假设以校正该组比特，其中当前假设定义了该组比特的不同比特状态和相关联的可靠性度量。如果对当前假设的解码不成功，则可以解码随后排序的假设，其中假设被排序使得其相关联的可靠性度量是单调非递减序列。解码可以迭代地进行，直到当前假设成功。

7. 发明申请

US20130212315A1 STATE RESPONSIVEOPERATIONS RELATING TO FLASH MEMORY CELLS 有权
标题翻译：与闪存存储器相关的状态响应
公开(公告)号：US20130212315A1
公开(公告)日：2013-08-15
申请号：US13369834
申请日：2012-02-09
申请人： Avi Steiner , Hanan Weingarten , Igal Maly , Avigdor Segal
发明人： Avi Steiner , Hanan Weingarten , Igal Maly , Avigdor Segal
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： A non-transitory computer readable medium, a flash controller and a method for state responsive encoding and programming; the method may include encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state.
摘要翻译：非暂时性计算机可读介质，闪存控制器和用于状态响应编码和编程的方法; 该方法可以包括通过应用状态响应编码过程来编码信息实体以提供至少一个码字; 其中所述状态响应编码处理响应闪存单元的状态; 以及通过应用响应于所述状态的状态响应编程处理，所述状态是估计状态或实际状态，将所述至少一个代码字编程到至少一组闪存单元。

8. 发明授权

US08850100B2 Interleaving codeword portions between multiple planes and/or dies of a flash memory device 有权
标题翻译：在闪速存储器件的多个平面和/或管芯之间交织码字部分
公开(公告)号：US08850100B2
公开(公告)日：2014-09-30
申请号：US13299276
申请日：2011-11-17
申请人： Avi Steiner , Hanan Weingarten , Guy Azrad , Avigdor Segal
发明人： Avi Steiner , Hanan Weingarten , Guy Azrad , Avigdor Segal
IPC分类号： G06F12/04 , G06F11/10 , G11C7/02 , G11C16/02
CPC分类号： G06F12/0246 , G06F12/0607 , G06F2212/7208
摘要： A system, a method and a non-transitory computer readable medium are disclosed. The non-transitory computer readable medium may store instructions for: (I) interleaving at least two portions of a first codeword of a group of codewords between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule; and (II) interleaving different portions of other codewords of the group of codewords between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. The at least two portions may be programmed to rows in different flash memory blocks, and the flash memory planes may belong to the same or multiple flash memory dies. The programming type ordering may define different decoupling sequence steps with sizes set for different programming types according to sensitivity to noise.
摘要翻译：公开了一种系统，方法和非暂时计算机可读介质。非暂时性计算机可读介质可以存储以下指令：（I）在至少两个闪速存储器平面之间交织一组码字的第一码字的至少两部分，同时违反（a）偶数的至少一个排序规则奇数排序规则，（b）编程类型排序规则，和（c）码字部分排序规则; 以及（II）在保持偶数奇数排序规则，编程类型排序规则和码字部分排序规则的同时，在多个闪速存储器层之间交织码字组的其他码字的不同部分。至少两个部分可以被编程为不同闪存块中的行，并且闪速存储器平面可以属于相同或多个闪速存储器管芯。编程类型排序可以根据对噪声的灵敏度来定义针对不同编程类型设置的尺寸的不同去耦序列步骤。

9. 发明授权

US08947941B2 State responsive operations relating to flash memory cells 有权
标题翻译：与闪存单元有关的状态响应操作
公开(公告)号：US08947941B2
公开(公告)日：2015-02-03
申请号：US13369834
申请日：2012-02-09
申请人： Avi Steiner , Hanan Weingarten , Igal Maly , Avigdor Segal
发明人： Avi Steiner , Hanan Weingarten , Igal Maly , Avigdor Segal
IPC分类号： G11C11/34
CPC分类号： G06F12/0246
摘要： A non-transitory computer readable medium, a flash controller and a method for state responsive encoding and programming; the method may include encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state.
摘要翻译：非暂时性计算机可读介质，闪存控制器和用于状态响应编码和编程的方法; 该方法可以包括通过应用状态响应编码过程来编码信息实体以提供至少一个码字; 其中所述状态响应编码处理响应闪存单元的状态; 以及通过应用响应于所述状态的状态响应编程处理，所述状态是估计状态或实际状态，将所述至少一个代码字编程到至少一组闪存单元。

10. 发明申请

US20120144093A1 INTERLEAVING CODEWORD PORTIONS BETWEEN MULTIPLE PLANES AND/OR DIES OF A FLASH MEMORY DEVICE 有权
标题翻译：闪存存储器件的多个平面和/或程序之间的交互编码区域
公开(公告)号：US20120144093A1
公开(公告)日：2012-06-07
申请号：US13299276
申请日：2011-11-17
申请人： Avi Steiner , Hanan Weingarten , Guy Azrad , Avigdor Segal
发明人： Avi Steiner , Hanan Weingarten , Guy Azrad , Avigdor Segal
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0607 , G06F2212/7208
摘要： A system, a method and non-transitory computer readable medium storing instructions for interleaving at least two portions of a first codeword of the group between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule and interleaving different portions of other codewords of the group between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule.
摘要翻译：一种存储指令的系统，方法和非暂时计算机可读介质，所述指令用于在至少两个闪速存储器平面之间交织所述组的第一码字的至少两个部分，同时违反（a）偶数奇数排序中的至少一个排序规则规则，（b）编程类型排序规则，以及（c）代码字部分排序规则并在多个快闪存储器平面之间交织该组的其他码字的不同部分，同时保持偶数奇数排序规则，编程类型排序规则和码字部分排序规则。

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