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1. 发明授权

US09921954B1 Method and system for split flash memory management between host and storage controller 有权
公开(公告)号：US09921954B1
公开(公告)日：2018-03-20
申请号：US13595848
申请日：2012-08-27
申请人： Erez Sabbag , Hanan Weingarten
发明人： Erez Sabbag , Hanan Weingarten
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0641 , G06F2212/1044 , G06F2212/7201 , G06F2212/7202 , G06F2212/7207 , G06F2212/7208
摘要： A computer readable medium, a system and a method for flash memory device that my store instructions for receiving from a host computer a first command that is a write command of a first data unit to a flash memory device, receiving, from the host computer, a second command that is indicative of a manner in which at least one entity out of (a) memory management metadata, (b) the first data unit and (c) at least one other data unit, should be stored in the flash memory device, and programming the at least one entity in the flash memory device in response to the second command.

2. 发明授权

US09063878B2 Method, system and computer readable medium for copy back 有权
标题翻译：用于复制的方法，系统和计算机可读介质
公开(公告)号：US09063878B2
公开(公告)日：2015-06-23
申请号：US13284794
申请日：2011-10-28
申请人： Erez Sabbag , Hanan Weingarten
发明人： Erez Sabbag , Hanan Weingarten
IPC分类号： G06F12/00 , G06F11/10 , G11C11/56 , G11C16/10
CPC分类号： G06F11/1072 , G11C11/5628 , G11C11/5671 , G11C16/102
摘要： Systems, computer readable media and methods for updating a flash memory device involve procedures for transferring, from a flash memory device to an external controller, only a portion of a data entity; and determining, by the external controller, based upon the portion of the data entity, whether to complete a copy back operation of the data entity or to correct errors of the data entity. If it is determined to correct errors of the data entity, then the procedure includes (a) completing a transfer of the data entity to the external controller; (b) error correcting the data entity to provide an amended data entity; and (c) writing the amended data entity to the flash memory device. If, however, it is determined to complete the copy back operation then the procedures includes completing the copy back operation of the data entity by transferring the data entity within the flash memory device.
摘要翻译：用于更新闪存设备的系统，计算机可读介质和方法涉及从闪速存储设备向外部控制器仅传输数据实体的一部分的过程; 以及由所述外部控制器基于所述数据实体的所述部分来确定是否完成所述数据实体的回传操作或者纠正所述数据实体的错误。如果确定纠正数据实体的错误，则该过程包括（a）完成数据实体向外部控制器的传送; （b）纠正数据实体以提供经修改的数据实体; 和（c）将经修改的数据实体写入闪存设备。然而，如果确定完成复制操作，则程序包括通过传送闪速存储器件内的数据实体完成数据实体的复制操作。

3. 发明授权

US08868821B2 Systems and methods for pre-equalization and code design for a flash memory 有权
标题翻译：用于闪存的预均衡和代码设计的系统和方法
公开(公告)号：US08868821B2
公开(公告)日：2014-10-21
申请号：US12836948
申请日：2010-07-15
申请人： Avi Steiner , Hanan Weingarten
发明人： Avi Steiner , Hanan Weingarten
IPC分类号： G06F12/00 , G11C11/56 , G06F11/10
CPC分类号： G06F11/1072 , G11C11/5628
摘要： A system, computer readable program, and method for programming flash memory, the method includes: providing multiple pairs of most significant bit (MSB) page uncoded bit error rates (UBERs) and least significant bit (LSB) page UBERs; selecting a selected MSB page code rate and a selected LSB page code rate so that a selected MSB page UBER associated with the selected MSB page code rate and a selected LSB page UBER associated with the selected LSB page code rate support a highest average UBER out of the multiple pairs of MSB page UBERs and LSB page UBERs, wherein the selected MSB page code rate and the selected LSB page code rate are obtainable under a desired code rate constraint; and determining an encoding and programming scheme that may be based on the selected MSB page UBER, the selected MSB code rate, the selected LSB page UBER and the selected LSB code rate.
摘要翻译：一种用于编程闪速存储器的系统，计算机可读程序和方法，所述方法包括：提供多对最高有效位（MSB）页未编码位错误率（UBER）和最低有效位（LSB）页面UBER）; 选择所选择的MSB页码和选择的LSB页码速率，使得与所选择的MSB页码速率相关联的所选择的MSB页面UBER和与所选择的LSB页码码率相关联的所选择的LSB页面UBER支持最高平均值UBER 多对MSB页面UBER和LSB页面UBER，其中所选择的MSB页面码率和所选择的LSB页面码率可以在期望的码率约束下获得; 以及确定可以基于所选择的MSB页面UBER，所选择的MSB码率，所选择的LSB页面UBER和所选择的LSB码率的编码和编程方案。

4. 发明授权

US08694715B2 Methods for adaptively programming flash memory devices and flash memory systems incorporating same 有权
标题翻译：自适应地编程闪存设备和并入其的闪存系统的方法
公开(公告)号：US08694715B2
公开(公告)日：2014-04-08
申请号：US12596680
申请日：2008-09-17
申请人： Hanan Weingarten , Erez Sabbag , Michael Katz
发明人： Hanan Weingarten , Erez Sabbag , Michael Katz
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C16/349
摘要： A method for programming a plurality of data sequences into a corresponding plurality of flash memory functional units using a programming process having at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, the method comprising providing at least one indication of at least one varying situational characteristic and determining a value for said at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, for each flash memory functional unit, depending at least partly on said indication of said varying characteristic; and, for each individual flash memory functional unit from among said plurality of flash memory functional units, programming a sequence of bits into said individual flash memory functional unit using a programming process having at least one selectable parameter, said at least one selectable parameter being set at said value determined for said individual flash memory functional unit.
摘要翻译：一种用于使用编程处理将多个数据序列编程到相应的多个闪速存储器功能单元中的方法，所述编程处理具有控制给定数据序列的编程过程的持续时间的至少一个可选择的编程持续时间控制参数，所述方法包括：至少一个变化的情境特征的指示，并且至少部分地基于每个闪存功能单元确定用于所述至少一个可选择的编程持续时间控制参数的值，用于控制给定数据序列的编程过程的持续时间所述指示所述变化的特征; 并且对于来自所述多个闪存功能单元的每个单独的闪速存储器功能单元，使用具有至少一个可选参数的编程处理将一系列比特编程到所述单独闪存功能单元中，所述至少一个可选参数被设置以所述个别闪存功能单元确定的所述值。

5. 发明授权

US08693258B2 Obtaining soft information using a hard interface 有权
标题翻译：使用硬接口获取软信息
公开(公告)号：US08693258B2
公开(公告)日：2014-04-08
申请号：US13370197
申请日：2012-02-09
申请人： Hanan Weingarten , Erez Sabbag
发明人： Hanan Weingarten , Erez Sabbag
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/26 , G11C16/349
摘要： A flash memory controller, a computer readable medium and a method for generating reliability information using a hard information interface, the method may include performing multiple read attempts, while using the hard information interface, of a plurality of flash memory cells to provide multiple read results; wherein each flash memory cell is read by providing a reference voltage to the flash memory cell; wherein a same reference voltage is provided during the multiple read attempts; and generating, for each flash memory cell, reliability information based upon multiple read results of the flash memory cell.
摘要翻译：闪速存储器控制器，计算机可读介质和使用硬信息接口产生可靠性信息的方法，所述方法可以包括在使用多个闪存单元的硬信息接口的同时执行多次读取尝试以提供多个读取结果 ; 其中通过向所述闪存单元提供参考电压来读取每个闪存单元; 其中在多个读取尝试期间提供相同的参考电压; 以及基于所述闪存单元的多个读取结果为每个闪存单元生成可靠性信息。

6. 发明授权

US08607124B2 System and method for setting a flash memory cell read threshold 有权
标题翻译：用于设置闪存单元读取阈值的系统和方法
公开(公告)号：US08607124B2
公开(公告)日：2013-12-10
申请号：US12973494
申请日：2010-12-20
申请人： Hanan Weingarten
发明人： Hanan Weingarten
IPC分类号： G11C29/00
CPC分类号： G11C11/5642 , G06F11/1048 , G11C16/26 , G11C16/3418
摘要： A system, method and computer readable medium for performing a first read attempt of multiple codeword portions while using a first read threshold candidate to provide multiple first read results, wherein the multiple codeword portions are stored in multiple flash memory cells; calculating a first read threshold candidate error correction decoding based score; wherein the calculating comprises error correction decoding of the multiple first read results; performing a second read attempt of the multiple codeword portions while using a second read threshold candidate to provide multiple second read results; calculating a second read threshold candidate error correction decoding based score; wherein the calculating comprises error correction decoding of the multiple second read results; and selecting a first read threshold out of the first and second read threshold candidates based on a relationship between the first and second read threshold candidate error correction decoding based scores.
摘要翻译：一种用于在使用第一读取阈值候选以提供多个第一读取结果的同时执行多个码字部分的第一读取尝试的系统，方法和计算机可读介质，其中所述多个码字部分存储在多个快闪存储器单元中; 计算第一读取阈值候选纠错解码基于分数; 其中所述计算包括所述多个第一读取结果的纠错解码; 在使用第二读取阈值候选以提供多个第二读取结果的同时执行所述多个码字部分的第二读取尝试; 计算第二读取阈值候选纠错解码基于分数; 其中所述计算包括所述多个第二读取结果的纠错解码; 以及基于所述第一和第二读取阈值候选纠错解码基于分数之间的关系从所述第一和第二读取阈值候选中选择第一读取阈值。

7. 发明授权

US08539311B2 System and method for data recovery in multi-level cell memories 有权
标题翻译：用于多级单元存储器中的数据恢复的系统和方法
公开(公告)号：US08539311B2
公开(公告)日：2013-09-17
申请号：US13117008
申请日：2011-05-26
申请人： Avi Steiner , Michael Katz , Hanan Weingarten , Erez Sabbag , Ofir Avraham Kanter , Avigdor Segal
发明人： Avi Steiner , Michael Katz , Hanan Weingarten , Erez Sabbag , Ofir Avraham Kanter , Avigdor Segal
IPC分类号： G11C29/00
CPC分类号： G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3404
摘要： A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level.
摘要翻译：提供了一种用于多级单元存储器件中的数据恢复的系统和方法。可以在存储器件中的多级单元的一个或多个相应级别中顺序编程一个或多个位。可以检测到在多级单元的后续第二级或更高级别中编程后续位的中断。可以从定义在第二或更高级别的编程中断之前编程的一个或多个位的多级单元恢复数据。

8. 发明授权

US08516274B2 Method, system and medium for analog encryption in a flash memory 有权
标题翻译：用于闪存中模拟加密的方法，系统和介质
公开(公告)号：US08516274B2
公开(公告)日：2013-08-20
申请号：US13081225
申请日：2011-04-06
申请人： Hanan Weingarten
发明人： Hanan Weingarten
IPC分类号： G06F11/30 , G06F12/14 , G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G06F12/1408 , G06F21/79 , G06F2221/2107 , G09C1/00 , G11C11/5621 , H04L9/065 , H04L9/14
摘要： A system and method for analog encryption and decryption. A threshold level encryption key stream is generated and a programming level for each bit of a cipher data stream, with each bit having a one or zero state, is determined, where a threshold for distinguishing between the one or zero state for each bit varies based on a corresponding entry in the threshold level encryption key steam. Each bit of the cipher data stream in a cell of a memory is programmed based on the programming level.
摘要翻译：一种用于模拟加密和解密的系统和方法。生成阈值级加密密钥流，并且确定每个比特具有一个或者零状态的密码数据流的每个比特的编程级别，其中用于区分每个比特的一个或者零个状态的阈值基于在阈值级加密密钥的相应条目中。存储器的单元中的密码数据流的每一位都是基于编程级编程的。

9. 发明授权

US08359516B2 Systems and methods for error correction and decoding on multi-level physical media 有权
标题翻译：用于多级物理介质上纠错和解码的系统和方法
公开(公告)号：US08359516B2
公开(公告)日：2013-01-22
申请号：US12667043
申请日：2008-09-17
申请人： Hanan Weingarten
发明人： Hanan Weingarten
IPC分类号： H03M13/00
CPC分类号： H03M13/19 , A61K36/8962 , G06F11/1008 , G06F11/1048 , H03M13/6566
摘要： Apparatus and methods for operating a flash device characterized by use of Lee distance based codes in a flash device so as to increase the number of errors that can be corrected for a given number of redundancy cells, compared with Hamming distance based codes.
摘要翻译：用于操作闪存设备的装置和方法，其特征在于在闪存设备中使用基于Lee距离的代码，以便与基于汉明距离的代码相比，增加对于给定数量的冗余单元可以校正的错误的数量。

10. 发明授权

US08341335B2 Flash memory apparatus with a heating system for temporarily retired memory portions 有权
标题翻译：具有用于临时退休存储器部分的加热系统的闪存装置
公开(公告)号：US08341335B2
公开(公告)日：2012-12-25
申请号：US12596446
申请日：2008-09-17
申请人： Hanan Weingarten , Shmuel Levy , Michael Katz
发明人： Hanan Weingarten , Shmuel Levy , Michael Katz
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F2212/1032 , G11C16/349
摘要： Flash memory apparatus including a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during the first duration of time, only to the certain portions, thereby to define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for the first duration of time.
摘要翻译：包括多个存储器部分的闪速存储装置以及在第一持续时间内至少在第一持续时间内仅保留来自所述多个存储器部分中的某些部分包括分配数据的操作的操作的控制器，，仅限于某些部分，从而将多个存储部分中的至少一个除了某些部分之外，作为第一持续时间的退休存储器部分。

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